Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1764469AbXJOWIW (ORCPT ); Mon, 15 Oct 2007 18:08:22 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1756242AbXJOWIE (ORCPT ); Mon, 15 Oct 2007 18:08:04 -0400 Received: from artax.karlin.mff.cuni.cz ([195.113.31.125]:41349 "EHLO artax.karlin.mff.cuni.cz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1763725AbXJOWID (ORCPT ); Mon, 15 Oct 2007 18:08:03 -0400 Date: Tue, 16 Oct 2007 00:08:01 +0200 (CEST) From: Mikulas Patocka To: Arjan van de Ven cc: Nick Piggin , Linux Kernel Mailing List Subject: Re: LFENCE instruction (was: [rfc][patch 3/3] x86: optimise barriers) In-Reply-To: <20071015143732.01d99af8@laptopd505.fenrus.org> Message-ID: References: <20071015143732.01d99af8@laptopd505.fenrus.org> X-Personality-Disorder: Schizoid MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1553 Lines: 38 > On Mon, 15 Oct 2007 22:47:42 +0200 (CEST) > Mikulas Patocka wrote: > > > > According to latest memory ordering specification documents from > > > Intel and AMD, both manufacturers are committed to in-order loads > > > from cacheable memory for the x86 architecture. Hence, smp_rmb() > > > may be a simple barrier. > > > > > > http://developer.intel.com/products/processor/manuals/318147.pdf > > > http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24593.pdf > > > > Hi > > > > I'm just wondering about one thing --- what is LFENCE instruction > > good for? > > > > SFENCE is for enforcing ordering in write-combining buffers (it > > doesn't have sense in write-back cache mode). > > MFENCE is for preventing of moving stores past loads. > > > > But what is LFENCE for? I read the above documents and they already > > say that CPUs have ordered loads. > > > > The cpus also have an explicit set of instructions that deliberately do > unordered stores/loads, and s/lfence etc are mostly designed for those. I know about unordered stores (movnti & similar) --- they basically use write-combining method on memory that is normally write-back --- and they need sfence. But which one instruction does unordered load and needs lefence? Mikulas - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/