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Date:   Fri, 9 Jun 2023 10:50:23 +0200
From:   Miquel Raynal <miquel.raynal@bootlin.com>
To:     Johan Jonker <jbx6244@gmail.com>
Cc:     richard@nod.at, vigneshr@ti.com, heiko@sntech.de,
        linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org,
        linux-rockchip@lists.infradead.org, yifeng.zhao@rock-chips.com
Subject: Re: [PATCH v1 3/5] mtd: nand: raw: rockchip-nand-controller: fix
 nand timing default
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In-Reply-To: <f8a10a00-c3e4-9749-789d-39fba7944646@gmail.com>
References: <19bf714a-43f9-c30a-8197-91aaaf4a6e5d@gmail.com>
        <f8a10a00-c3e4-9749-789d-39fba7944646@gmail.com>
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Hi Johan,

jbx6244@gmail.com wrote on Thu, 8 Jun 2023 18:30:40 +0200:

> Somehow not all NAND chips give a valid timing setting with the
> nand_get_sdr_timings() function.

nand_get_sdr_timings() is a core function and is not particularly
clever. All chips are supposed to support SDR mode 0 so if you chip
does not advertises that the chip is broken, not the controller. This
must be fixed in the chip manufacturer driver, not in the controller
driver.

> Don't consider it as an error,
> but fall back to the default value in order to continue to use
> the driver.
>=20
> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> ---
>  drivers/mtd/nand/raw/rockchip-nand-controller.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
>=20
> diff --git a/drivers/mtd/nand/raw/rockchip-nand-controller.c b/drivers/mt=
d/nand/raw/rockchip-nand-controller.c
> index f56430f6c..e39431cfa 100644
> --- a/drivers/mtd/nand/raw/rockchip-nand-controller.c
> +++ b/drivers/mtd/nand/raw/rockchip-nand-controller.c
> @@ -429,8 +429,10 @@ static int rk_nfc_setup_interface(struct nand_chip *=
chip, int target,
>  		return 0;
>=20
>  	timings =3D nand_get_sdr_timings(conf);
> -	if (IS_ERR(timings))
> -		return -EOPNOTSUPP;
> +	if (IS_ERR(timings)) {
> +		rknand->timing =3D 0x1081;

This is way to magical anyway :)

> +		return 0;
> +	}
>=20
>  	if (IS_ERR(nfc->nfc_clk))
>  		rate =3D clk_get_rate(nfc->ahb_clk);
> --
> 2.30.2
>=20


Thanks,
Miqu=C3=A8l