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Date:   Fri, 9 Jun 2023 17:55:34 +0200
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Subject: Re: [PATCH v2 0/4] arm64: dts: mediatek: mt8186: More DVFS nodes
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To:     Chen-Yu Tsai <wenst@chromium.org>,
        AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@collabora.com>
Cc:     devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org,
        linux-mediatek@lists.infradead.org,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>
References: <20230609072906.2784594-1-wenst@chromium.org>
From:   Matthias Brugger <matthias.bgg@gmail.com>
In-Reply-To: <20230609072906.2784594-1-wenst@chromium.org>
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On 09/06/2023 09:29, Chen-Yu Tsai wrote:
> Hi,
> 
> This adds more of the DVFS stuff at the SoC .dtsi level. This includes
> the CCI and GPU.
> 
> Changes since v1:
> - Dropped opp-level property from CPU and CCI OPP tables
> - Used "opp-supported-hw = <0xff>" for GPU base OPPs to denote "all
>    variations"
> 
> Please have a look and merge for this cycle if possible.
> 
> On another note, I'm still cleaning up the MT6366 regulator's binding.
> We shouldn't upstream the boards until the PMIC is ready.
> 
> ChenYu
> 
> Chen-Yu Tsai (4):
>    arm64: dts: mediatek: mt8186: Add CCI node and CCI OPP table
>    arm64: dts: mediatek: mt8186: Wire up CPU frequency/voltage scaling
>    arm64: dts: mediatek: mt8186: Add GPU speed bin NVMEM cells
>    arm64: dts: mediatek: mt8186: Wire up GPU voltage/frequency scaling
> 
>   arch/arm64/boot/dts/mediatek/mt8186.dtsi | 490 ++++++++++++++++++++++-
>   1 file changed, 489 insertions(+), 1 deletion(-)
> 

Series applied,
thanks!