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Date:   Sun, 11 Jun 2023 17:04:03 +0100
From:   "Russell King (Oracle)" <linux@armlinux.org.uk>
To:     =?utf-8?B?QXLEsW7DpyDDnE5BTA==?= <arinc9.unal@gmail.com>
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Subject: Re: [PATCH net v2 1/7] net: dsa: mt7530: fix trapping frames with
 multiple CPU ports on MT7531
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On Sun, Jun 11, 2023 at 11:15:41AM +0300, Arınç ÜNAL wrote:
> Every bit of the CPU port bitmap for MT7531 and the switch on the MT7988
> SoC represents a CPU port to trap frames to. These switches trap frames to
> the CPU port the user port, which the frames are received from, is affine
> to.

I think you need to reword that, because at least I went "err what" -
especially the second sentence!

> Currently, only the bit that corresponds to the first found CPU port is set
> on the bitmap.

Ok.

> When multiple CPU ports are being used, frames from the user
> ports affine to the other CPU port which are set to be trapped will be
> dropped as the affine CPU port is not set on the bitmap.

Hmm. I think this is trying to say:

"When multiple CPU ports are being used, trapped frames from user ports
not affine to the first CPU port will be dropped we do not set these
ports as being affine to the second CPU port."

> Only the MT7531
> switch is affected as there's only one port to be used as a CPU port on the
> switch on the MT7988 SoC.

Erm, hang on. The previous bit indicated there was a problem when there
are multiple CPU ports, but here you're saying that only one switch is
affected - and that switch has only one CPU port. This at the very least
raises eyebrows, because it's just contradicted the first part
explaining when there's a problem.

> diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c
> index 9bc54e1348cb..8ab4718abb06 100644
> --- a/drivers/net/dsa/mt7530.c
> +++ b/drivers/net/dsa/mt7530.c
> @@ -1010,6 +1010,14 @@ mt753x_cpu_port_enable(struct dsa_switch *ds, int port)
>  	if (priv->id == ID_MT7621)
>  		mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port));
>  
> +	/* Add the CPU port to the CPU port bitmap for MT7531 and the switch on
> +	 * the MT7988 SoC. Any frames set for trapping to CPU port will be
> +	 * trapped to the CPU port the user port, which the frames are received
> +	 * from, is affine to.

Please reword the second sentence.

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