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From:   Adam Ford <aford173@gmail.com>
Date:   Sun, 11 Jun 2023 12:02:42 -0500
Message-ID: <CAHCN7xLPKa2hrBMC1kaJkxVL9NC+c1TWgcQHMBPefnvxGPTCwQ@mail.gmail.com>
Subject: Re: [PATCH] clk: imx: composite-8m: Add imx8m_divider_determine_rate
To:     Fabio Estevam <festevam@gmail.com>
Cc:     linux-clk@vger.kernel.org, aford@beaconembedded.com,
        Abel Vesa <abelvesa@kernel.org>, Peng Fan <peng.fan@nxp.com>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Shawn Guo <shawnguo@kernel.org>,
        Sascha Hauer <s.hauer@pengutronix.de>,
        Pengutronix Kernel Team <kernel@pengutronix.de>,
        NXP Linux Team <linux-imx@nxp.com>,
        "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" 
        <linux-arm-kernel@lists.infradead.org>,
        open list <linux-kernel@vger.kernel.org>,
        Maxime Ripard <maxime@cerno.tech>
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On Tue, Jun 6, 2023 at 1:45=E2=80=AFPM Fabio Estevam <festevam@gmail.com> w=
rote:
>
> On Sat, May 6, 2023 at 4:53=E2=80=AFPM Adam Ford <aford173@gmail.com> wro=
te:
> >
> > Currently, certain clocks are derrived as a divider from their
> > parent clock.  For some clocks, even when CLK_SET_RATE_PARENT
> > is set, the parent clock is not properly set which can lead
> > to some relatively inaccurate clock values.
> >

+ Maxime

> > Unlike imx/clk-composite-93 and imx/clk-divider-gate, it
> > cannot rely on calling a standard determine_rate function,
> > because the 8m composite clocks have a pre-divider and
> > post-divider. Because of this, a custom determine_rate
> > function is necessary to determine the maximum clock
> > division which is equivalent to pre-divider * the
> > post-divider.
> >
> > With this added, the system can attempt to adjust the parent rate
> > when the proper flags are set which can lead to a more precise clock
> > value.
> >
> > On the imx8mplus, no clock changes are present.
> > On the Mini and Nano, this can help achieve more accurate
> > lcdif clocks. When trying to get a pixel clock of 31.500MHz
> > on an imx8m Nano, the clocks divided the 594MHz down, but
> > left the parent rate untouched which caused a calulation error.
> >
> > Before:
> > video_pll              594000000
> >   video_pll_bypass     594000000
> >     video_pll_out      594000000
> >       disp_pixel       31263158
> >         disp_pixel_clk 31263158
> >
> > Variance =3D -236842 Hz
> >
> > After this patch:
> > video_pll               31500000
> >   video_pll_bypass      31500000
> >     video_pll_out       31500000
> >       disp_pixel        31500000
> >         disp_pixel_clk  31500000
> >
> > Variance =3D 0 Hz
> >
> > All other clocks rates and parent were the same.
> > Similar results on imx8mm were found.
> >
> > Fixes: 690dccc4a0bf ("Revert "clk: imx: composite-8m: Add support to de=
termine_rate"")
> > Signed-off-by: Adam Ford <aford173@gmail.com>
>

Peng / Abel,

Any suggestions on how we can move this forward?  Looking at the
clk-composite-8m driver, imx8m_clk_composite_compute_dividers uses the
max values which is basically what my patch does.  There was some
discussion about making determine_rate mandatory for muxes[1] and this
patch should help with this in addition to making it easier to sync
more video resolutions on the 8m Mini and Nano.

adam
[1] - https://www.spinics.net/lists/alsa-devel/msg157914.html


> This works fine on my imx8mm-evk, so:
>
> Tested-by: Fabio Estevam <festevam@gmail.com>