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From:   David Laight <David.Laight@ACULAB.COM>
To:     "'kirill.shutemov@linux.intel.com'" <kirill.shutemov@linux.intel.com>,
        "Huang, Kai" <kai.huang@intel.com>
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        "Wysocki, Rafael J" <rafael.j.wysocki@intel.com>,
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        "Chatre, Reinette" <reinette.chatre@intel.com>,
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        "Williams, Dan J" <dan.j.williams@intel.com>
Subject: RE: [PATCH v11 18/20] x86: Handle TDX erratum to reset TDX private
 memory during kexec() and reboot
Thread-Topic: [PATCH v11 18/20] x86: Handle TDX erratum to reset TDX private
 memory during kexec() and reboot
Thread-Index: AQHZnSRWXDaSmJ22okO690LL2Ubsg6+HJc9w
Date:   Mon, 12 Jun 2023 13:18:01 +0000
Message-ID: <fc4930150f3242e69dcb007c0b23cfd2@AcuMS.aculab.com>
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From: kirill.shutemov@linux.intel.com
> Sent: 12 June 2023 12:49
> 
> On Mon, Jun 12, 2023 at 10:27:44AM +0000, Huang, Kai wrote:
> > Does it make sense?
> 
> I understand your logic. AFAICS, it is correct (smp_mb() instead of __mb()
> would be better), but it is not justified from complexity PoV.

Given that x86 performs writes pretty much in code order.
Do you need anything more than a compile barrier?

> This lockless exercise gave me a pause to understand.
> 
> Lockless doesn't buy you anything here, only increases complexity.
> Just take a lock.

Indeed...

	David

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