Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
From:   Heiko =?ISO-8859-1?Q?St=FCbner?= <heiko@sntech.de>
To:     guoren@kernel.org, Palmer Dabbelt <palmer@dabbelt.com>
Cc:     linux-riscv@lists.infradead.org, samuel@sholland.org,
        christoph.muellner@vrull.eu,
        Conor Dooley <conor.dooley@microchip.com>,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH RFC 0/2] RISC-V: T-Head vector handling
Date:   Mon, 12 Jun 2023 17:44:04 +0200
Message-ID: <2408420.NG923GbCHz@diego>
In-Reply-To: <mhng-ca852a2c-a1c7-4b14-a9a2-f2bd4541d6b7@palmer-ri-x1c9>
References: <mhng-ca852a2c-a1c7-4b14-a9a2-f2bd4541d6b7@palmer-ri-x1c9>
MIME-Version: 1.0
Content-Transfer-Encoding: 7Bit
Content-Type: text/plain; charset="us-ascii"
Precedence: bulk

Hi,

Am Montag, 12. Juni 2023, 17:29:49 CEST schrieb Palmer Dabbelt:
> On Tue, 14 Mar 2023 22:29:41 PDT (-0700), Palmer Dabbelt wrote:
> > On Tue, 28 Feb 2023 13:54:33 PST (-0800), heiko@sntech.de wrote:
> >> From: Heiko Stuebner <heiko.stuebner@vrull.eu>
> >>
> >> As is widely known the T-Head C9xx cores used for example in the
> >> Allwinner D1 implement an older non-ratified variant of the vector spec.
> >>
> >> While userspace will probably have a lot more problems implementing
> >> support for both, on the kernel side the needed changes are actually
> >> somewhat small'ish and can be handled via alternatives somewhat nicely.
> >>
> >> With this patchset I could run the same userspace program (picked from
> >> some riscv-vector-test repository) that does some vector additions on
> >> both qemu and a d1-nezha board. On both platforms it ran sucessfully and
> >> even produced the same results.
> >>
> >>
> >> As can be seen in the todo list, there are 2 places where the changed
> >> SR_VS location still needs to be handled in the next revision
> >> (assembly + ALTERNATIVES + constants + probably stringify resulted in
> >>  some grey hair so far already)
> >>
> >>
> >> ToDo:
> >> - follow along with the base vector patchset
> >> - handle SR_VS access in _save_context and _secondary_start_sbi
> >>
> >>
> >> Heiko Stuebner (2):
> >>   RISC-V: define the elements of the VCSR vector CSR
> >>   RISC-V: add T-Head vector errata handling
> >>
> >>  arch/riscv/Kconfig.erratas           |  13 +++
> >>  arch/riscv/errata/thead/errata.c     |  32 ++++++
> >>  arch/riscv/include/asm/csr.h         |  31 +++++-
> >>  arch/riscv/include/asm/errata_list.h |  62 +++++++++++-
> >>  arch/riscv/include/asm/vector.h      | 139 +++++++++++++++++++++++++--
> >>  5 files changed, 261 insertions(+), 16 deletions(-)
> >
> > I have no opposition to calling the T-Head vector stuff an errata
> > against V, the RISC-V folks have already made it quite apparent that
> > anything goes here.  I would like to get the standard V uABI sorted out
> > first, though, as there's still a lot of moving pieces there.  It's kind
> > of hard here as T-Head got thrown under the bus, but I'm not sure what
> > else to do about it.
> 
> The V-1.0 support has been merged, so I think we're good to go.  Does 
> someone mind re-spinning this against for-next so it lines up with all 
> the new user interfaces?

glad to hear that. I found the merge message now as well.
Somehow I was only Cc'ed on individual patches but not on the
cover-letter, so didn't realize the merge till now.

I'll try to re-spin and adapt to the changes since the initial submission.

Heiko


 I'll try to re-spin and adapt to the changes that
happened since the original submission.