Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
Date:   Mon, 12 Jun 2023 13:29:10 -0700
From:   Dan Williams <dan.j.williams@intel.com>
To:     Terry Bowman <terry.bowman@amd.com>, <alison.schofield@intel.com>,
        <vishal.l.verma@intel.com>, <ira.weiny@intel.com>,
        <bwidawsk@kernel.org>, <dan.j.williams@intel.com>,
        <dave.jiang@intel.com>, <Jonathan.Cameron@huawei.com>,
        <linux-cxl@vger.kernel.org>
CC:     <terry.bowman@amd.com>, <rrichter@amd.com>,
        <linux-kernel@vger.kernel.org>, <bhelgaas@google.com>
Subject: RE: [PATCH v5 23/26] cxl/pci: Disable root port interrupts in RCH
 mode
Message-ID: <64878016974b0_1433ac29473@dwillia2-xfh.jf.intel.com.notmuch>
References: <20230607221651.2454764-1-terry.bowman@amd.com>
 <20230607221651.2454764-24-terry.bowman@amd.com>
Content-Type: text/plain; charset="us-ascii"
Content-Disposition: inline
In-Reply-To: <20230607221651.2454764-24-terry.bowman@amd.com>
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?s56q4pHKZOUMl4aG3hbkHfVr8r2y+5q8o9QG7iPAJ0W5DTbodRmjlogoZgxm?=
 =?us-ascii?Q?Jcab6HG+f6nuPkhDapR4jNKySL0pQOUzBMwRSCc1e3Lan0iRlQGNNdwQ9gl3?=
 =?us-ascii?Q?pJWMp5mo7jP9mZLX0IzBEtotY69jyQHxt97fxix/54d+Qo3VcoxReVJTWUmh?=
 =?us-ascii?Q?efWeL3UPyyAiu6NpJpnPQH1MZE4yFjNMg2Nh1Bnqf+HpkQiGgLNzhQFWQg0d?=
 =?us-ascii?Q?lLGBYdeO+E1gnY14t39YyHvIMf535CjZgiyMFt6VUqxEmfjrnY8wB0x7lIfT?=
 =?us-ascii?Q?7ulZDvaadSP7JcIThk29IiEzR6GIrymoa4tVftAqc5T/NYcUEM6cIeC90UoP?=
 =?us-ascii?Q?VgXn9IdYc5NM0RmAzRRKqOrhg9Gz5pqOQOcq0ZtTrq3w2uUhOjm6JrefrjG+?=
 =?us-ascii?Q?xYEmCMHyLQXseYcWOLVT8RQVyg0b6brftJdOdaSQRNMZgZec6tTC8Fue0iF2?=
 =?us-ascii?Q?gJ1J1sfnWmhjsPAw4vRNQvWlz7XCouipoKPtY3JaZw+XE2emv62CRkL4bShr?=
 =?us-ascii?Q?93ssha+qjIXJkkdXQuBUhxYRMcB+jiqUrMEuZHMGJbqgJauuxgObBbUP+dmU?=
 =?us-ascii?Q?Pq7Dz0HqspXV2LCPEUQX8h3/V7AnFyrVzb5gZgfwdjTmRMVSApn+BoQ48+yQ?=
 =?us-ascii?Q?3rXP5BdkTaSVP439gF85c+r1ugoCXiJRyqTcKkbReDvT6NKTM9eAbd0esOh+?=
 =?us-ascii?Q?CYxbWva1sVZj5nbAHaLsM27bWDGs18Ql/2rUDgDyIraAos9pwOXh7CWxKd0/?=
 =?us-ascii?Q?DohEcI1nFS9obpFjLQqZJ3O5+14zediFb4k4uX2UBVSsNuRcrB9/tYQiEFzS?=
 =?us-ascii?Q?CWn6RSBCc8msU2b+dqic96zMTvzkycptauzMf7qIqaUV8kqnUiQx+BHAXHU8?=
 =?us-ascii?Q?6PWz5YvntmGM7EkNTUzNDOMHb5HOpDylk1Rq1XzKMXLsQHarHzFJ2C2k6Yot?=
 =?us-ascii?Q?PRacG1hJ4uNhTVC9xDEEKWdunP7c+KBHhevyM419kMjxLHFe83Ss3J6f1e35?=
 =?us-ascii?Q?e9PinljJU2SbiTFx2abFTAcAD4BulS5A7XkLrM77hHdha9V6Pep5ym6DRHN3?=
 =?us-ascii?Q?ZejQgVD0uteEuxJyvZRn+AmSopwJLMhBLWH3vMydIW7d0PW8lyjoQEoI2uDK?=
 =?us-ascii?Q?jhrzzePnM+o+TN8EPMIinMsg3K19kNaf6EWHMRvLCEJZ25Thj1HUUy8DcWaN?=
 =?us-ascii?Q?YwlOogACziwV0+ASAw57M1x7hC99XjmIEo+Y62SDxlo2zHzhVP65sp1UF/4U?=
 =?us-ascii?Q?7kyZZaVYhcR02FEDC/2LZMCjmp0wadV7+RVEcac2BYROoX4UpRAmHJ+YZgI6?=
 =?us-ascii?Q?xQorvgQoVFEEdjVdtRX+KYvLIWzgUfwbw26gP4eYgMwpmDJQOjotPnt41WgG?=
 =?us-ascii?Q?lDvyUguKD2f1NRhWiBPIHqxJa92i/ANQ2dTH8nJRw/MtunJzdb4kR0afrAb9?=
 =?us-ascii?Q?TjBNj5PeGAfgu5BfgrR2vWkonLFHGGf13Ftbfuc+rqkMIVk6iubOSQWRZ6y3?=
 =?us-ascii?Q?o3XJBTGCjE8SSJCTCwnn4jaqzr7TYj9aVaTalwEzQE3XOBzBXDcFN+mTJmIp?=
 =?us-ascii?Q?GSuTIiXa5WUl/p7ICvymOLSqXoNA4/ip1ePooc+kwJEK6AOjC7LyGJjjXq6D?=
 =?us-ascii?Q?vw=3D=3D?=
X-MS-Exchange-CrossTenant-Network-Message-Id: 97e5911a-d49c-44a4-a390-08db6b83afc0
X-MS-Exchange-CrossTenant-AuthSource: PH8PR11MB8107.namprd11.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jun 2023 20:29:13.8296
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: i+qxSoIMly1smb/bHwjzW64JLf0qDmOYH2IbSMlFHQzMaYdRXTGstGUdkSlpp7BO/Ogv/dRn8gbkzv1e8vcR4NsYnnSLRMZ7e3ZfjwO3HBk=
X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR11MB5271
X-OriginatorOrg: intel.com
X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,
        DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,
        SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham
        autolearn_force=no version=3.4.6
X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on
        lindbergh.monkeyblade.net
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

Terry Bowman wrote:
> The RCH root port contains root command AER registers that should not be
> enabled.[1] Disable these to prevent root port interrupts.
> 
> [1] CXL 3.0 - 12.2.1.1 RCH Downstream Port-detected Errors
> 
> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> ---
>  drivers/cxl/core/port.c | 26 ++++++++++++++++++++++++++
>  1 file changed, 26 insertions(+)
> 
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index bc5d0ee9da54..828ae69086c4 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -981,6 +981,30 @@ static int cxl_dport_map_regs(struct cxl_dport *dport)
>  	return cxl_dport_map_rch_aer(dport);
>  }
>  
> +static void cxl_disable_rch_root_ints(struct cxl_dport *dport)
> +{
> +	void __iomem *aer_base = dport->regs.dport_aer;
> +	u32 aer_cmd_mask, aer_cmd;
> +
> +	if (!dport->rch || !aer_base)
> +		return;

Does this need to check ->rch? There is no path that sets
->regs.dport_aer in the VH case, right?

> +
> +	/*
> +	 * Disable RCH root port command interrupts.
> +	 * CXL 3.0 12.2.1.1 - RCH Downstream Port-detected Errors
> +	 *
> +	 * This sequnce may not be necessary. CXL spec states disabling
> +	 * the root cmd register's interrupts is required. But, PCI spec
> +	 * shows these are disabled by default on reset.
> +	 */
> +	aer_cmd_mask = (PCI_ERR_ROOT_CMD_COR_EN |
> +			PCI_ERR_ROOT_CMD_NONFATAL_EN |
> +			PCI_ERR_ROOT_CMD_FATAL_EN);
> +	aer_cmd = readl(aer_base + PCI_ERR_ROOT_COMMAND);
> +	aer_cmd &= ~aer_cmd_mask;
> +	writel(aer_cmd, aer_base + PCI_ERR_ROOT_COMMAND);

What about the scenario where @host_bridge->native_cxl_error is false?
Should the driver unconditionally touch AER registers?

> +}
> +
>  static struct cxl_dport *
>  __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev,
>  		     int port_id, resource_size_t component_reg_phys,
> @@ -1038,6 +1062,8 @@ __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev,
>  	if (rc && rc != -ENODEV)
>  		return ERR_PTR(rc);
>  
> +	cxl_disable_rch_root_ints(dport);
> +

It feels odd to modify hardware state within an object setup helper. Is
there a reason this needs to be settled before __devm_cxl_add_dport()
returns? If not this feels like a helper that cxl_acpi should call to
change the state of the @dport instance it allocated.