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McKenney" To: linux-kernel@vger.kernel.org Cc: gwml@vger.gnuweeb.org, kernel-team@meta.com, w@lwt.eu, Zhangjin Wu , Willy Tarreau , "Paul E . McKenney" Subject: [PATCH v2 nolibc 16/53] tools/nolibc: riscv: Fix up load/store instructions for rv32 Date: Mon, 12 Jun 2023 13:44:37 -0700 Message-Id: <20230612204514.292087-16-paulmck@kernel.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <8b757cc0-3719-4e63-a755-9710384137bc@paulmck-laptop> References: <8b757cc0-3719-4e63-a755-9710384137bc@paulmck-laptop> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Zhangjin Wu When compile nolibc application for rv32, we got such errors: nolibc/sysroot/riscv/include/arch.h:190: Error: unrecognized opcode `ld a4,0(a3)' nolibc/sysroot/riscv/include/arch.h:194: Error: unrecognized opcode `sd a3,%lo(_auxv)(a4)' nolibc/sysroot/riscv/include/arch.h:196: Error: unrecognized opcode `sd a2,%lo(environ)(a3)' Refer to arch/riscv/include/asm/asm.h and add REG_L/REG_S macros here to let rv32 uses its own lw/sw instructions. Signed-off-by: Zhangjin Wu Signed-off-by: Willy Tarreau Signed-off-by: Paul E. McKenney --- tools/include/nolibc/arch-riscv.h | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/tools/include/nolibc/arch-riscv.h b/tools/include/nolibc/arch-riscv.h index 0d5f15fdedc4..992a1739dd9c 100644 --- a/tools/include/nolibc/arch-riscv.h +++ b/tools/include/nolibc/arch-riscv.h @@ -33,9 +33,13 @@ struct sys_stat_struct { #if __riscv_xlen == 64 #define PTRLOG "3" #define SZREG "8" +#define REG_L "ld" +#define REG_S "sd" #elif __riscv_xlen == 32 #define PTRLOG "2" #define SZREG "4" +#define REG_L "lw" +#define REG_S "sw" #endif /* Syscalls for RISCV : @@ -181,7 +185,7 @@ void __attribute__((weak,noreturn,optimize("omit-frame-pointer"))) _start(void) ".option norelax\n" "lla gp, __global_pointer$\n" ".option pop\n" - "lw a0, 0(sp)\n" /* argc (a0) was in the stack */ + REG_L" a0, 0(sp)\n" /* argc (a0) was in the stack */ "add a1, sp, "SZREG"\n" /* argv (a1) = sp */ "slli a2, a0, "PTRLOG"\n" /* envp (a2) = SZREG*argc ... */ "add a2, a2, "SZREG"\n" /* + SZREG (skip null) */ @@ -189,14 +193,14 @@ void __attribute__((weak,noreturn,optimize("omit-frame-pointer"))) _start(void) "add a3, a2, zero\n" /* iterate a3 over envp to find auxv (after NULL) */ "0:\n" /* do { */ - "ld a4, 0(a3)\n" /* a4 = *a3; */ + REG_L" a4, 0(a3)\n" /* a4 = *a3; */ "add a3, a3, "SZREG"\n" /* a3 += sizeof(void*); */ "bne a4, zero, 0b\n" /* } while (a4); */ "lui a4, %hi(_auxv)\n" /* a4 = &_auxv (high bits) */ - "sd a3, %lo(_auxv)(a4)\n" /* store a3 into _auxv */ + REG_S" a3, %lo(_auxv)(a4)\n" /* store a3 into _auxv */ - "lui a3, %hi(environ)\n" /* a3 = &environ (high bits) */ - "sd a2,%lo(environ)(a3)\n" /* store envp(a2) into environ */ + "lui a3, %hi(environ)\n" /* a3 = &environ (high bits) */ + REG_S" a2,%lo(environ)(a3)\n"/* store envp(a2) into environ */ "andi sp,a1,-16\n" /* sp must be 16-byte aligned */ "call main\n" /* main() returns the status code, we'll exit with it. */ "li a7, 93\n" /* NR_exit == 93 */ -- 2.40.1