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Date:   Tue, 13 Jun 2023 09:52:51 +0200
From:   Marc Kleine-Budde <mkl@pengutronix.de>
To:     Srinivas Goud <srinivas.goud@amd.com>
Cc:     wg@grandegger.com, davem@davemloft.net, edumazet@google.com,
        kuba@kernel.org, pabeni@redhat.com, gcnu.goud@gmail.com,
        git@amd.com, michal.simek@xilinx.com, linux-can@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/3] dt-bindings: can: xilinx_can: Add ECC =?utf-8?Q?p?=
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On 12.06.2023 17:12:55, Srinivas Goud wrote:
> ECC feature added to Tx and Rx FIFO=E2=80=99s for Xilinx CAN Controller.
> Part of this feature configuration and counter registers
> added in IP for 1bit/2bit ECC errors.
> Please find more details in PG096 v5.1 document.
>=20
> xlnx,has-ecc is optional property and added to Xilinx CAN
> Controller node if ECC block enabled in the HW.
>=20
> Signed-off-by: Srinivas Goud <srinivas.goud@amd.com>

Is there a way to introspect the IP core to check if this feature is
compiled in?

Marc

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