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From:   "Mukesh Savaliya (QUIC)" <quic_msavaliy@quicinc.com>
To:     "Praveen Talari (QUIC)" <quic_ptalari@quicinc.com>,
        "agross@kernel.org" <agross@kernel.org>,
        "andersson@kernel.org" <andersson@kernel.org>,
        "konrad.dybcio@linaro.org" <konrad.dybcio@linaro.org>,
        "broonie@kernel.org" <broonie@kernel.org>,
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        "linux-spi@vger.kernel.org" <linux-spi@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
CC:     "Mukesh Savaliya (QUIC)" <quic_msavaliy@quicinc.com>,
        "Visweswara Tanuku (QUIC)" <quic_vtanuku@quicinc.com>,
        "Vijaya Krishna Nivarthi (Temp) (QUIC)" <quic_vnivarth@quicinc.com>,
        "Aniket RANDIVE (QUIC)" <quic_arandive@quicinc.com>
Subject: RE: [PATCH 1/2] soc: qcom: geni-se: Add SPI SLAVE mode support for
 GENI based QuPv3
Thread-Topic: [PATCH 1/2] soc: qcom: geni-se: Add SPI SLAVE mode support for
 GENI based QuPv3
Thread-Index: AQHZncPKGvyzmiHkJkS+nMVuNJLseK+ImiYA
Date:   Tue, 13 Jun 2023 11:35:30 +0000
Message-ID: <BY5PR02MB6770F5A65ADF5899920CDC60E655A@BY5PR02MB6770.namprd02.prod.outlook.com>
References: <20230613065229.5619-1-quic_ptalari@quicinc.com>
 <20230613065229.5619-2-quic_ptalari@quicinc.com>
In-Reply-To: <20230613065229.5619-2-quic_ptalari@quicinc.com>
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> -----Original Message-----
> From: Praveen Talari (QUIC)
> Sent: Tuesday, June 13, 2023 12:22 PM
> To: agross@kernel.org; andersson@kernel.org; konrad.dybcio@linaro.org;
> broonie@kernel.org; linux-arm-msm@vger.kernel.org; linux-
> spi@vger.kernel.org; linux-kernel@vger.kernel.org
> Cc: Mukesh Savaliya (QUIC) <quic_msavaliy@quicinc.com>; Visweswara
> Tanuku (QUIC) <quic_vtanuku@quicinc.com>; Vijaya Krishna Nivarthi (Temp)
> (QUIC) <quic_vnivarth@quicinc.com>; Aniket RANDIVE (QUIC)
> <quic_arandive@quicinc.com>; Praveen Talari (QUIC)
> <quic_ptalari@quicinc.com>
> Subject: [PATCH 1/2] soc: qcom: geni-se: Add SPI SLAVE mode support for
> GENI based QuPv3
>=20
> Add SPI SLAVE mode support for GENI based QuPv3.
>=20
> Signed-off-by: Praveen Talari <quic_ptalari@quicinc.com>

Looks good to me.

Reviewed-by: Mukesh Kumar Savaliya <quic_msavaliy@quicinc.com>

> ---
>  include/linux/soc/qcom/geni-se.h | 9 +++++++++
>  1 file changed, 9 insertions(+)
>=20
> diff --git a/include/linux/soc/qcom/geni-se.h
> b/include/linux/soc/qcom/geni-se.h
> index 821a19135bb6..29e06905bc1f 100644
> --- a/include/linux/soc/qcom/geni-se.h
> +++ b/include/linux/soc/qcom/geni-se.h
> @@ -35,6 +35,7 @@ enum geni_se_protocol_type {
>  	GENI_SE_UART,
>  	GENI_SE_I2C,
>  	GENI_SE_I3C,
> +	GENI_SE_SPI_SLAVE,
>  };
>=20
>  struct geni_wrapper;
> @@ -73,12 +74,14 @@ struct geni_se {
>=20
>  /* Common SE registers */
>  #define GENI_FORCE_DEFAULT_REG		0x20
> +#define GENI_OUTPUT_CTRL		0x24
>  #define SE_GENI_STATUS			0x40
>  #define GENI_SER_M_CLK_CFG		0x48
>  #define GENI_SER_S_CLK_CFG		0x4c
>  #define GENI_IF_DISABLE_RO		0x64
>  #define GENI_FW_REVISION_RO		0x68
>  #define SE_GENI_CLK_SEL			0x7c
> +#define SE_GENI_CFG_SEQ_START		0x84
>  #define SE_GENI_DMA_MODE_EN		0x258
>  #define SE_GENI_M_CMD0			0x600
>  #define SE_GENI_M_CMD_CTRL_REG		0x604
> @@ -111,6 +114,9 @@ struct geni_se {
>  /* GENI_FORCE_DEFAULT_REG fields */
>  #define FORCE_DEFAULT	BIT(0)
>=20
> +/* GENI_OUTPUT_CTRL fields */
> +#define GENI_IO_MUX_0_EN		BIT(0)
> +
>  /* GENI_STATUS fields */
>  #define M_GENI_CMD_ACTIVE		BIT(0)
>  #define S_GENI_CMD_ACTIVE		BIT(12)
> @@ -130,6 +136,9 @@ struct geni_se {
>  /* GENI_CLK_SEL fields */
>  #define CLK_SEL_MSK			GENMASK(2, 0)
>=20
> +/* SE_GENI_CFG_SEQ_START fields */
> +#define START_TRIGGER			BIT(0)
> +
>  /* SE_GENI_DMA_MODE_EN */
>  #define GENI_DMA_MODE_EN		BIT(0)
>=20
> --
> 2.17.1