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Date:   Tue, 13 Jun 2023 12:41:55 -0500
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Subject: Re: [PATCH v8 0/2] Enable multiple MCAN on AM62x
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From:   Judith Mendez <jm@ti.com>
To:     <linux-can@vger.kernel.org>, Marc Kleine-Budde <mkl@pengutronix.de>
CC:     Wolfgang Grandegger <wg@grandegger.com>,
        "David S . Miller" <davem@davemloft.net>,
        Eric Dumazet <edumazet@google.com>,
        Jakub Kicinski <kuba@kernel.org>,
        Paolo Abeni <pabeni@redhat.com>, <netdev@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>, Schuyler Patton <spatton@ti.com>,
        Tero Kristo <kristo@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        <devicetree@vger.kernel.org>,
        Oliver Hartkopp <socketcan@hartkopp.net>,
        Simon Horman <simon.horman@corigine.com>,
        Conor Dooley <conor+dt@linaro.org>,
        Tony Lindgren <tony@atomide.com>,
        Chandrasekar Ramakrishnan <rcsekar@samsung.com>
References: <20230530224820.303619-1-jm@ti.com>
In-Reply-To: <20230530224820.303619-1-jm@ti.com>
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Hi all,

On 5/30/23 5:48 PM, Judith Mendez wrote:
> On AM62x there are two MCANs in MCU domain. The MCANs in MCU domain
> were not enabled since there is no hardware interrupt routed to A53
> GIC interrupt controller. Therefore A53 Linux cannot be interrupted
> by MCU MCANs.
> 
> This solution instantiates a hrtimer with 1 ms polling interval
> for MCAN device when there is no hardware interrupt property in
> DTB MCAN node. The hrtimer generates a recurring software interrupt
> which allows to call the isr. The isr will check if there is pending
> transaction by reading a register and proceed normally if there is.
> MCANs with hardware interrupt routed to A53 Linux will continue to
> use the hardware interrupt as expected.
> 
> Timer polling method was tested on both classic CAN and CAN-FD
> at 125 KBPS, 250 KBPS, 1 MBPS and 2.5 MBPS with 4 MBPS bitrate
> switching.
> 
> Letency and CPU load benchmarks were tested on 3x MCAN on AM62x.
> 1 MBPS timer polling interval is the better timer polling interval
> since it has comparable latency to hardware interrupt with the worse
> case being 1ms + CAN frame propagation time and CPU load is not
> substantial. Latency can be improved further with less than 1 ms
> polling intervals, howerver it is at the cost of CPU usage since CPU
> load increases at 0.5 ms.
> 
> Note that in terms of power, enabling MCU MCANs with timer-polling
> implementation might have negative impact since we will have to wake
> up every 1 ms whether there are CAN packets pending in the RX FIFO or
> not. This might prevent the CPU from entering into deeper idle states
> for extended periods of time.

Was wondering if I am still pending some updates for this patch series? 
Or if any other issues please let me know. (: Thanks all

~ Judith