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Message-ID: <83be6c80-adb6-2670-1d65-769a7fbe8a98@quicinc.com>
Date:   Wed, 14 Jun 2023 16:29:37 +0530
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Subject: Re: [PATCH 2/2] arm64: dts: qcom: ipq5332: add support for the RDP446
 variant
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To:     Konrad Dybcio <konrad.dybcio@linaro.org>, <agross@kernel.org>,
        <andersson@kernel.org>, <robh+dt@kernel.org>,
        <krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org>,
        <linux-arm-msm@vger.kernel.org>, <devicetree@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>
CC:     <quic_srichara@quicinc.com>, <quic_sjaganat@quicinc.com>,
        <quic_kathirav@quicinc.com>, <quic_arajkuma@quicinc.com>,
        <quic_anusha@quicinc.com>
References: <20230606095732.12884-1-quic_harihk@quicinc.com>
 <20230606095732.12884-3-quic_harihk@quicinc.com>
 <0848ee8e-f520-06a1-9a15-f6dadc2fd69e@linaro.org>
From:   Hariharan K <quic_harihk@quicinc.com>
In-Reply-To: <0848ee8e-f520-06a1-9a15-f6dadc2fd69e@linaro.org>
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ipq5332-rdp-common.dtsi will be posted shortly. This patch will be 
re-based on top of it.

Regards,
Hariharan K

On 6/14/2023 4:13 PM, Konrad Dybcio wrote:
> 
> 
> On 6.06.2023 11:57, Hariharan K wrote:
>> Add the initial device tree support for the Reference Design
>> Platform(RDP) 446 based on IPQ5332 family of SoC. This patch carries
>> the support for Console UART, SPI NOR and I2C.
>>
>> Signed-off-by: Hariharan K <quic_harihk@quicinc.com>
>> ---
> Please consider making a common dtsi, like for 9574 here:
> 
> https://lore.kernel.org/linux-arm-msm/20230614085040.22071-1-quic_anusha@quicinc.com
> 
> Konrad
>>   arch/arm64/boot/dts/qcom/Makefile           |  1 +
>>   arch/arm64/boot/dts/qcom/ipq5332-rdp446.dts | 83 +++++++++++++++++++++
>>   2 files changed, 84 insertions(+)
>>   create mode 100644 arch/arm64/boot/dts/qcom/ipq5332-rdp446.dts
>>
>> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
>> index 4f9e81253e18..f962e1b7cf7a 100644
>> --- a/arch/arm64/boot/dts/qcom/Makefile
>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>> @@ -6,6 +6,7 @@ dtb-$(CONFIG_ARCH_QCOM)	+= apq8096-db820c.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= apq8096-ifc6640.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= ipq5332-mi01.2.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= ipq5332-rdp442.dtb
>> +dtb-$(CONFIG_ARCH_QCOM)	+= ipq5332-rdp446.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= ipq5332-rdp468.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= ipq6018-cp01-c1.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk01.dtb
>> diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp446.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp446.dts
>> new file mode 100644
>> index 000000000000..0e1d98b093e4
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp446.dts
>> @@ -0,0 +1,83 @@
>> +// SPDX-License-Identifier: BSD-3-Clause
>> +/*
>> + * IPQ5332 AP-MI04.1 board device tree source
>> + *
>> + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "ipq5332.dtsi"
>> +
>> +/ {
>> +	model = "Qualcomm Technologies, Inc. IPQ5332 MI04.1";
>> +	compatible = "qcom,ipq5332-ap-mi04.1", "qcom,ipq5332";
>> +
>> +	aliases {
>> +		serial0 = &blsp1_uart0;
>> +	};
>> +
>> +	chosen {
>> +		stdout-path = "serial0";
>> +	};
>> +};
>> +
>> +&blsp1_uart0 {
>> +	pinctrl-0 = <&serial_0_pins>;
>> +	pinctrl-names = "default";
>> +	status = "okay";
>> +};
>> +
>> +&blsp1_i2c1 {
>> +	clock-frequency  = <400000>;
>> +	pinctrl-0 = <&i2c_1_pins>;
>> +	pinctrl-names = "default";
>> +	status = "okay";
>> +};
>> +
>> +&blsp1_spi0 {
>> +	pinctrl-0 = <&spi_0_data_clk_pins &spi_0_cs_pins>;
>> +	pinctrl-names = "default";
>> +	status = "okay";
>> +
>> +	flash@0 {
>> +		compatible = "micron,n25q128a11", "jedec,spi-nor";
>> +		reg = <0>;
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +		spi-max-frequency = <50000000>;
>> +	};
>> +};
>> +
>> +&sleep_clk {
>> +	clock-frequency = <32000>;
>> +};
>> +
>> +&xo_board {
>> +	clock-frequency = <24000000>;
>> +};
>> +
>> +/* PINCTRL */
>> +
>> +&tlmm {
>> +	i2c_1_pins: i2c-1-state {
>> +		pins = "gpio29", "gpio30";
>> +		function = "blsp1_i2c0";
>> +		drive-strength = <8>;
>> +		bias-pull-up;
>> +	};
>> +
>> +	spi_0_data_clk_pins: spi-0-data-clk-state {
>> +		pins = "gpio14", "gpio15", "gpio16";
>> +		function = "blsp0_spi";
>> +		drive-strength = <2>;
>> +		bias-pull-down;
>> +	};
>> +
>> +	spi_0_cs_pins: spi-0-cs-state {
>> +		pins = "gpio17";
>> +		function = "blsp0_spi";
>> +		drive-strength = <2>;
>> +		bias-pull-up;
>> +	};
>> +};