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d="scan'208";a="824876952" Received: from smile.fi.intel.com ([10.237.72.54]) by fmsmga002.fm.intel.com with ESMTP; 14 Jun 2023 09:22:39 -0700 Received: from andy by smile.fi.intel.com with local (Exim 4.96) (envelope-from ) id 1q9TGZ-003jp9-1Y; Wed, 14 Jun 2023 19:22:39 +0300 Date: Wed, 14 Jun 2023 19:22:39 +0300 From: Andy Shevchenko To: Raag Jadav Cc: linus.walleij@linaro.org, mika.westerberg@linux.intel.com, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, mallikarjunappa.sangannavar@intel.com, pandith.n@intel.com Subject: Re: [PATCH v3 2/3] pinctrl: intel: refine ->irq_set_type() hook Message-ID: References: <20230613085054.10976-1-raag.jadav@intel.com> <20230613085054.10976-3-raag.jadav@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230613085054.10976-3-raag.jadav@intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Jun 13, 2023 at 02:20:53PM +0530, Raag Jadav wrote: > Utilize a temporary variable for common shift operation > in ->irq_set_type() hook and improve readability. > While at it, simplify if-else-if chain and save a few bytes. > > add/remove: 0/0 grow/shrink: 0/1 up/down: 0/-16 (-16) > Function old new delta > intel_gpio_irq_type 317 301 -16 > Total: Before=10469, After=10453, chg -0.15% ... > value = readl(reg); > - > value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV); > > if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { > - value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT; > + rxevcfg = PADCFG0_RXEVCFG_EDGE_BOTH; > } else if (type & IRQ_TYPE_EDGE_FALLING) { > - value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT; > - value |= PADCFG0_RXINV; > + rxevcfg = PADCFG0_RXEVCFG_EDGE; > } else if (type & IRQ_TYPE_EDGE_RISING) { > - value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT; > + rxevcfg = PADCFG0_RXEVCFG_EDGE; > } else if (type & IRQ_TYPE_LEVEL_MASK) { > - if (type & IRQ_TYPE_LEVEL_LOW) > - value |= PADCFG0_RXINV; > + rxevcfg = PADCFG0_RXEVCFG_LEVEL; > } else { > - value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT; > + rxevcfg = PADCFG0_RXEVCFG_DISABLED; > } > > + if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW) > + value |= PADCFG0_RXINV; > + > + value |= rxevcfg << PADCFG0_RXEVCFG_SHIFT; > writel(value, reg); Looking at this I realized that entire temporary variable assignments can be done outside of spin lock. You probably would need another one for keeping rxinv value. Will it give us any memory reduction in comparison to the current code? -- With Best Regards, Andy Shevchenko