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Date:   Thu, 15 Jun 2023 01:20:09 +0530
From:   Akhil P Oommen <quic_akhilpo@quicinc.com>
To:     Konrad Dybcio <konrad.dybcio@linaro.org>
CC:     Rob Clark <robdclark@gmail.com>,
        Abhinav Kumar <quic_abhinavk@quicinc.com>,
        Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
        Sean Paul <sean@poorly.run>, David Airlie <airlied@gmail.com>,
        Daniel Vetter <daniel@ffwll.ch>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Bjorn Andersson <andersson@kernel.org>,
        Konrad Dybcio <konrad.dybcio@somainline.org>,
        Conor Dooley <conor+dt@kernel.org>,
        <linux-arm-msm@vger.kernel.org>, <dri-devel@lists.freedesktop.org>,
        <freedreno@lists.freedesktop.org>, <devicetree@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>, Rob Clark <robdclark@chromium.org>,
        Marijn Suijten <marijn.suijten@somainline.org>
Subject: Re: [PATCH v8 16/18] drm/msm/a6xx: Use adreno_is_aXYZ macros in
 speedbin matching
Message-ID: <u74y24z3jmklfyx7zvmiw3oakejm3t253tcs2kmrupl6l3qqpa@3rsubk6pkz5b>
References: <20230223-topic-gmuwrapper-v8-0-69c68206609e@linaro.org>
 <20230223-topic-gmuwrapper-v8-16-69c68206609e@linaro.org>
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In-Reply-To: <20230223-topic-gmuwrapper-v8-16-69c68206609e@linaro.org>
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On Mon, May 29, 2023 at 03:52:35PM +0200, Konrad Dybcio wrote:
> 
> Before transitioning to using per-SoC and not per-Adreno speedbin
> fuse values (need another patchset to land elsewhere), a good
> improvement/stopgap solution is to use adreno_is_aXYZ macros in
> place of explicit revision matching. Do so to allow differentiating
> between A619 and A619_holi.
> 
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com>

-Akhil
> ---
>  drivers/gpu/drm/msm/adreno/a6xx_gpu.c   | 18 +++++++++---------
>  drivers/gpu/drm/msm/adreno/adreno_gpu.h | 14 ++++++++++++--
>  2 files changed, 21 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index 5faa85543428..ca4ffa44097e 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -2163,23 +2163,23 @@ static u32 adreno_7c3_get_speed_bin(u32 fuse)
>  	return UINT_MAX;
>  }
>  
> -static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse)
> +static u32 fuse_to_supp_hw(struct device *dev, struct adreno_gpu *adreno_gpu, u32 fuse)
>  {
>  	u32 val = UINT_MAX;
>  
> -	if (adreno_cmp_rev(ADRENO_REV(6, 1, 8, ANY_ID), rev))
> +	if (adreno_is_a618(adreno_gpu))
>  		val = a618_get_speed_bin(fuse);
>  
> -	else if (adreno_cmp_rev(ADRENO_REV(6, 1, 9, ANY_ID), rev))
> +	else if (adreno_is_a619(adreno_gpu))
>  		val = a619_get_speed_bin(fuse);
>  
> -	else if (adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), rev))
> +	else if (adreno_is_7c3(adreno_gpu))
>  		val = adreno_7c3_get_speed_bin(fuse);
>  
> -	else if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev))
> +	else if (adreno_is_a640(adreno_gpu))
>  		val = a640_get_speed_bin(fuse);
>  
> -	else if (adreno_cmp_rev(ADRENO_REV(6, 5, 0, ANY_ID), rev))
> +	else if (adreno_is_a650(adreno_gpu))
>  		val = a650_get_speed_bin(fuse);
>  
>  	if (val == UINT_MAX) {
> @@ -2192,7 +2192,7 @@ static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse)
>  	return (1 << val);
>  }
>  
> -static int a6xx_set_supported_hw(struct device *dev, struct adreno_rev rev)
> +static int a6xx_set_supported_hw(struct device *dev, struct adreno_gpu *adreno_gpu)
>  {
>  	u32 supp_hw;
>  	u32 speedbin;
> @@ -2211,7 +2211,7 @@ static int a6xx_set_supported_hw(struct device *dev, struct adreno_rev rev)
>  		return ret;
>  	}
>  
> -	supp_hw = fuse_to_supp_hw(dev, rev, speedbin);
> +	supp_hw = fuse_to_supp_hw(dev, adreno_gpu, speedbin);
>  
>  	ret = devm_pm_opp_set_supported_hw(dev, &supp_hw, 1);
>  	if (ret)
> @@ -2330,7 +2330,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
>  
>  	a6xx_llc_slices_init(pdev, a6xx_gpu);
>  
> -	ret = a6xx_set_supported_hw(&pdev->dev, config->rev);
> +	ret = a6xx_set_supported_hw(&pdev->dev, adreno_gpu);
>  	if (ret) {
>  		a6xx_destroy(&(a6xx_gpu->base.base));
>  		return ERR_PTR(ret);
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> index 7a5d595d4b99..21513cec038f 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -268,9 +268,9 @@ static inline int adreno_is_a630(struct adreno_gpu *gpu)
>  	return gpu->revn == 630;
>  }
>  
> -static inline int adreno_is_a640_family(struct adreno_gpu *gpu)
> +static inline int adreno_is_a640(struct adreno_gpu *gpu)
>  {
> -	return (gpu->revn == 640) || (gpu->revn == 680);
> +	return gpu->revn == 640;
>  }
>  
>  static inline int adreno_is_a650(struct adreno_gpu *gpu)
> @@ -289,6 +289,11 @@ static inline int adreno_is_a660(struct adreno_gpu *gpu)
>  	return gpu->revn == 660;
>  }
>  
> +static inline int adreno_is_a680(struct adreno_gpu *gpu)
> +{
> +	return gpu->revn == 680;
> +}
> +
>  /* check for a615, a616, a618, a619 or any derivatives */
>  static inline int adreno_is_a615_family(struct adreno_gpu *gpu)
>  {
> @@ -306,6 +311,11 @@ static inline int adreno_is_a650_family(struct adreno_gpu *gpu)
>  	return gpu->revn == 650 || gpu->revn == 620 || adreno_is_a660_family(gpu);
>  }
>  
> +static inline int adreno_is_a640_family(struct adreno_gpu *gpu)
> +{
> +	return adreno_is_a640(gpu) || adreno_is_a680(gpu);
> +}
> +
>  u64 adreno_private_address_space_size(struct msm_gpu *gpu);
>  int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
>  		     uint32_t param, uint64_t *value, uint32_t *len);
> 
> -- 
> 2.40.1
>