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Date:   Thu, 15 Jun 2023 01:48:40 +0530
From:   Akhil P Oommen <quic_akhilpo@quicinc.com>
To:     Konrad Dybcio <konrad.dybcio@linaro.org>
CC:     Rob Clark <robdclark@gmail.com>,
        Abhinav Kumar <quic_abhinavk@quicinc.com>,
        Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
        Sean Paul <sean@poorly.run>, David Airlie <airlied@gmail.com>,
        Daniel Vetter <daniel@ffwll.ch>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Bjorn Andersson <andersson@kernel.org>,
        Konrad Dybcio <konrad.dybcio@somainline.org>,
        Conor Dooley <conor+dt@kernel.org>,
        <linux-arm-msm@vger.kernel.org>, <dri-devel@lists.freedesktop.org>,
        <freedreno@lists.freedesktop.org>, <devicetree@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>, Rob Clark <robdclark@chromium.org>,
        Marijn Suijten <marijn.suijten@somainline.org>
Subject: Re: [PATCH v8 18/18] drm/msm/a6xx: Add A610 speedbin support
Message-ID: <ab2yzsjp65t53wp5nytjuc7eb74zklkb6i342bc5edhm45j3qm@kpyq52is7tde>
References: <20230223-topic-gmuwrapper-v8-0-69c68206609e@linaro.org>
 <20230223-topic-gmuwrapper-v8-18-69c68206609e@linaro.org>
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In-Reply-To: <20230223-topic-gmuwrapper-v8-18-69c68206609e@linaro.org>
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On Mon, May 29, 2023 at 03:52:37PM +0200, Konrad Dybcio wrote:
> 
> A610 is implemented on at least three SoCs: SM6115 (bengal), SM6125
> (trinket) and SM6225 (khaje). Trinket does not support speed binning
> (only a single SKU exists) and we don't yet support khaje upstream.
> Hence, add a fuse mapping table for bengal to allow for per-chip
> frequency limiting.
> 
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>  drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 27 +++++++++++++++++++++++++++
>  1 file changed, 27 insertions(+)
> 
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index d046af5f6de2..c304fa118cff 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -2098,6 +2098,30 @@ static bool a6xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
>  	return progress;
>  }
>  
> +static u32 a610_get_speed_bin(u32 fuse)
> +{
> +	/*
> +	 * There are (at least) three SoCs implementing A610: SM6125 (trinket),
> +	 * SM6115 (bengal) and SM6225 (khaje). Trinket does not have speedbinning,
> +	 * as only a single SKU exists and we don't support khaje upstream yet.
> +	 * Hence, this matching table is only valid for bengal and can be easily
> +	 * expanded if need be.
> +	 */
> +
> +	if (fuse == 0)
> +		return 0;
> +	else if (fuse == 206)
> +		return 1;
> +	else if (fuse == 200)
> +		return 2;
> +	else if (fuse == 157)
> +		return 3;
> +	else if (fuse == 127)
> +		return 4;
> +
> +	return UINT_MAX;
> +}
> +
>  static u32 a618_get_speed_bin(u32 fuse)
>  {
>  	if (fuse == 0)
> @@ -2195,6 +2219,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct adreno_gpu *adreno_gpu, u3
>  {
>  	u32 val = UINT_MAX;
>  
> +	if (adreno_is_a610(adreno_gpu))
> +		val = a610_get_speed_bin(fuse);
> +

Didn't you update here to convert to 'else if' in one of the earlier
patches??

Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com>

-Akhil.
>  	if (adreno_is_a618(adreno_gpu))
>  		val = a618_get_speed_bin(fuse);
>  
> 
> -- 
> 2.40.1
>