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charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: ih5BCgpsRHHfz1-gprherO3N1ZKCCMvq X-Proofpoint-GUID: ih5BCgpsRHHfz1-gprherO3N1ZKCCMvq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-14_14,2023-06-14_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 spamscore=0 priorityscore=1501 lowpriorityscore=0 bulkscore=0 adultscore=0 impostorscore=0 suspectscore=0 phishscore=0 mlxscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306140181 X-Spam-Status: No, score=-2.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,RCVD_IN_DNSWL_LOW, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 6/14/2023 12:54 PM, Abhinav Kumar wrote: > > > On 6/14/2023 12:35 PM, Abhinav Kumar wrote: >> >> >> On 6/14/2023 5:23 AM, Marijn Suijten wrote: >>> On 2023-06-14 15:01:59, Dmitry Baryshkov wrote: >>>> On 14/06/2023 14:42, Marijn Suijten wrote: >>>>> On 2023-06-13 18:57:11, Jessica Zhang wrote: >>>>>> DPU 5.x+ supports a databus widen mode that allows more data to be >>>>>> sent >>>>>> per pclk. Enable this feature flag on all relevant chipsets. >>>>>> >>>>>> Signed-off-by: Jessica Zhang >>>>>> --- >>>>>>    drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 ++- >>>>>>    drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 ++ >>>>>>    2 files changed, 4 insertions(+), 1 deletion(-) >>>>>> >>>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >>>>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >>>>>> index 36ba3f58dcdf..0be7bf0bfc41 100644 >>>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >>>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >>>>>> @@ -103,7 +103,8 @@ >>>>>>        (BIT(DPU_INTF_INPUT_CTRL) | \ >>>>>>         BIT(DPU_INTF_TE) | \ >>>>>>         BIT(DPU_INTF_STATUS_SUPPORTED) | \ >>>>>> -     BIT(DPU_DATA_HCTL_EN)) >>>>>> +     BIT(DPU_DATA_HCTL_EN) | \ >>>>>> +     BIT(DPU_INTF_DATABUS_WIDEN)) >>>>> >>>>> This doesn't work.  DPU 5.0.0 is SM8150, which has DSI 6G 2.3.  In the >>>>> last patch for DSI you state and enable widebus for DSI 6G 2.5+ only, >>>>> meaning DPU and DSI are now desynced, and the output is completely >>>>> corrupted. >>> I looked at the internal docs and also this change. This change is incorrect because this will try to enable widebus for DPU >= 5.0 and DSI >= 2.5 That was not the intended right condition as thats not what the docs say. We should enable for DPU >= 7.0 and DSI >= 2.5 Is there any combination where this compatibility is broken? That would be the strange thing for me ( not DPU 5.0 and DSI 2.5 as that was incorrect) Part of this confusion is because of catalog macro re-use again. This series is a good candidate and infact I think we should only do core_revision based check on DPU and DSI to avoid bringing the catalog mess into this. >>> Tested this on SM8350 which actually has DSI 2.5, and it is also >>> corrupted with this series so something else on this series might be >>> broken. >>> > > Missed this response. That seems strange. > > This series was tested on SM8350 HDK with a command mode panel. > > We will fix the DPU-DSI handshake and post a v2 but your issue needs > investigation in parallel. > > So another bug to track that would be great. > >>>>> Is the bound in dsi_host wrong, or do DPU and DSI need to communicate >>>>> when widebus will be enabled, based on DPU && DSI supporting it? >>>> >>>> I'd prefer to follow the second approach, as we did for DP. DPU asks >>>> the >>>> actual video output driver if widebus is to be enabled. >>> >> >> I was afraid of this. This series was made on an assumption that the >> DPU version of widebus and DSI version of widebus would be compatible >> but looks like already SM8150 is an outlier. >> >> Yes, I think we have to go with second approach. >> >> DPU queries DSI if it supports widebus and enables it. >> >> Thanks for your responses. We will post a v2. >> >>> Doesn't it seem very strange that DPU 5.x+ comes with a widebus feature, >>> but the DSI does not until two revisions later?  Or is this available on >>> every interface, but only for a different (probably DP) encoder block? >>> >> >> Yes its strange. >> I have clarified this above. Its not strange but appeared strange because we were checking wrong conditions. >>> - Marijn