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Date:   Thu, 15 Jun 2023 00:40:47 +0300
From:   =?UTF-8?B?QXLEsW7DpyDDnE5BTA==?= <arinc.unal@arinc9.com>
To:     Vladimir Oltean <olteanv@gmail.com>
CC:     Daniel Golle <daniel@makrotopia.org>,
        Landen Chao <Landen.Chao@mediatek.com>,
        DENG Qingfang <dqfext@gmail.com>,
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        "David S. Miller" <davem@davemloft.net>,
        Eric Dumazet <edumazet@google.com>,
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        Matthias Brugger <matthias.bgg@gmail.com>,
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        <angelogioacchino.delregno@collabora.com>,
        Russell King <linux@armlinux.org.uk>,
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Subject: =?US-ASCII?Q?Re=3A_=5BPATCH_net_v4_1/7=5D_net=3A_dsa=3A_mt7530=3A_fix_tr?= =?US-ASCII?Q?apping_frames_with_multiple_CPU_ports_on_MT7531?=
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On 15 June 2023 00:13:52 EEST, Vladimir Oltean <olteanv@gmail=2Ecom> wrote:
>On Wed, Jun 14, 2023 at 11:56:44PM +0300, Ar=C4=B1n=C3=A7 =C3=9CNAL wrote=
:
>> On 14=2E06=2E2023 22:43, Vladimir Oltean wrote:
>> > On Mon, Jun 12, 2023 at 10:59:39AM +0300, arinc9=2Eunal@gmail=2Ecom w=
rote:
>> > > From: Ar=C4=B1n=C3=A7 =C3=9CNAL <arinc=2Eunal@arinc9=2Ecom>
>> > >=20
>> > > Every bit of the CPU port bitmap for MT7531 and the switch on the M=
T7988
>> > > SoC represents a CPU port to trap frames to=2E These switches trap =
frames
>> > > received from a user port to the CPU port that is affine to the use=
r port
>> > > from which the frames are received=2E
>> > >=20
>> > > Currently, only the bit that corresponds to the first found CPU por=
t is set
>> > > on the bitmap=2E When multiple CPU ports are being used, the trappe=
d frames
>> > > from the user ports not affine to the first CPU port will be droppe=
d as the
>> > > other CPU port is not set on the bitmap=2E The switch on the MT7988=
 SoC is
>> > > not affected as there's only one port to be used as a CPU port=2E
>> > >=20
>> > > To fix this, introduce the MT7531_CPU_PMAP macro to individually se=
t the
>> > > bits of the CPU port bitmap=2E Set the CPU port bitmap for MT7531 a=
nd the
>> > > switch on the MT7988 SoC on mt753x_cpu_port_enable() which runs on =
a loop
>> > > for each CPU port=2E
>> > >=20
>> > > Add a comment to explain frame trapping for these switches=2E
>> > >=20
>> > > According to the document MT7531 Reference Manual for Development B=
oard
>> > > v1=2E0, the MT7531_CPU_PMAP bits are unset after reset so no need t=
o clear it
>> > > beforehand=2E Since there's currently no public document for the sw=
itch on
>> > > the MT7988 SoC, I assume this is also the case for this switch=2E
>> > >=20
>> > > Fixes: c288575f7810 ("net: dsa: mt7530: Add the support of MT7531 s=
witch")
>> > > Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL <arinc=2Eunal@arinc9=2Ecom=
>
>> > > ---
>> >=20
>> > Would you agree that this is just preparatory work for change "net: d=
sa:
>> > introduce preferred_default_local_cpu_port and use on MT7530" and not=
 a
>> > fix to an existing problem in the code base?
>>=20
>> Makes sense=2E Pre-preferred_default_local_cpu_port patch, there isn't =
a case
>> where there's a user port affine to a CPU port that is not enabled on t=
he
>> CPU port bitmap=2E So yeah, this is just preparatory work for "net: dsa=
:
>> introduce preferred_default_local_cpu_port and use on MT7530"=2E
>>=20
>> So how do I change the patch to reflect this?
>>=20
>> Ar=C4=B1n=C3=A7
>
>net: dsa: mt7530: set all CPU ports in MT7531_CPU_PMAP
>
>MT7531_CPU_PMAP represents the destination port mask for trapped-to-CPU
>frames (further restricted by PCR_MATRIX)=2E
>
>Currently the driver sets the first CPU port as the single port in this
>bit mask, which works fine regardless of whether the device tree defines
>port 5, 6 or 5+6 as CPU ports=2E This is because the logic coincides with
>DSA's logic of picking the first CPU port as the CPU port that all user
>ports are affine to, by default=2E
>
>An upcoming change would like to influence DSA's selection of the
>default CPU port to no longer be the first one, and in that case, this
>logic needs adaptation=2E
>
>Since there is no observed leakage or duplication of frames if all CPU
>ports are defined in this bit mask, simply include them all=2E
>
>Note that there is no Fixes tag

Thanks a lot for making it easier for me=2E

Ar=C4=B1n=C3=A7