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[2620:137:e000::1:20]) by mx.google.com with ESMTP id x27-20020aa79a5b000000b0065e445224e5si8513301pfj.332.2023.06.15.00.32.34; Thu, 15 Jun 2023 00:32:45 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244865AbjFOHSK (ORCPT + 99 others); Thu, 15 Jun 2023 03:18:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41506 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244147AbjFOHRd (ORCPT ); Thu, 15 Jun 2023 03:17:33 -0400 Received: from relay2-d.mail.gandi.net (relay2-d.mail.gandi.net [217.70.183.194]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AA1602954; Thu, 15 Jun 2023 00:16:57 -0700 (PDT) X-GND-Sasl: alex@ghiti.fr X-GND-Sasl: alex@ghiti.fr X-GND-Sasl: alex@ghiti.fr X-GND-Sasl: alex@ghiti.fr X-GND-Sasl: alex@ghiti.fr X-GND-Sasl: alex@ghiti.fr X-GND-Sasl: alex@ghiti.fr X-GND-Sasl: alex@ghiti.fr X-GND-Sasl: alex@ghiti.fr X-GND-Sasl: alex@ghiti.fr X-GND-Sasl: alex@ghiti.fr X-GND-Sasl: alex@ghiti.fr X-GND-Sasl: alex@ghiti.fr X-GND-Sasl: alex@ghiti.fr X-GND-Sasl: alex@ghiti.fr X-GND-Sasl: alex@ghiti.fr X-GND-Sasl: alex@ghiti.fr X-GND-Sasl: alex@ghiti.fr X-GND-Sasl: alex@ghiti.fr X-GND-Sasl: alex@ghiti.fr X-GND-Sasl: alex@ghiti.fr X-GND-Sasl: alex@ghiti.fr X-GND-Sasl: alex@ghiti.fr Received: by mail.gandi.net (Postfix) with ESMTPSA id 81EB640003; Thu, 15 Jun 2023 07:16:51 +0000 (UTC) Message-ID: <25c378d3-8914-4f24-8ea9-0e2204c90727@ghiti.fr> Date: Thu, 15 Jun 2023 09:16:51 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH v2 03/10] riscv: Make legacy counter enum match the HW numbering Content-Language: en-US To: Andrew Jones , Alexandre Ghiti Cc: Jonathan Corbet , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Ian Rogers , Paul Walmsley , Palmer Dabbelt , Albert Ou , Atish Patra , Anup Patel , Will Deacon , Rob Herring , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org References: <20230512085321.13259-1-alexghiti@rivosinc.com> <20230512085321.13259-4-alexghiti@rivosinc.com> <20230531-ddb2d631e152526102f41d5e@orel> From: Alexandre Ghiti In-Reply-To: <20230531-ddb2d631e152526102f41d5e@orel> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-2.7 required=5.0 tests=BAYES_00,NICE_REPLY_A, RCVD_IN_DNSWL_LOW,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 31/05/2023 16:01, Andrew Jones wrote: > On Fri, May 12, 2023 at 10:53:14AM +0200, Alexandre Ghiti wrote: >> RISCV_PMU_LEGACY_INSTRET used to be set to 1 whereas the offset of this >> hardware counter from CSR_CYCLE is actually 2: make this offset match the >> real hw offset so that we can directly expose those values to userspace. >> >> Signed-off-by: Alexandre Ghiti >> --- >> drivers/perf/riscv_pmu_legacy.c | 7 +++++-- >> 1 file changed, 5 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/perf/riscv_pmu_legacy.c b/drivers/perf/riscv_pmu_legacy.c >> index ca9e20bfc7ac..0d8c9d8849ee 100644 >> --- a/drivers/perf/riscv_pmu_legacy.c >> +++ b/drivers/perf/riscv_pmu_legacy.c >> @@ -12,8 +12,11 @@ >> #include >> #include >> >> -#define RISCV_PMU_LEGACY_CYCLE 0 >> -#define RISCV_PMU_LEGACY_INSTRET 1 >> +enum { >> + RISCV_PMU_LEGACY_CYCLE, >> + RISCV_PMU_LEGACY_TIME, >> + RISCV_PMU_LEGACY_INSTRET >> +}; > I guess this doesn't hurt, since these are just indices internal to this > driver, but it's a bit odd to also have a RISCV_PMU_LEGACY_TIME, when > the driver is only for cycle and instret, as its Kconfig help text says. I understand and you're right, that's weird, so I'll change that with the following: diff --git a/drivers/perf/riscv_pmu_legacy.c b/drivers/perf/riscv_pmu_legacy.c index ca9e20bfc7ac..6a000abc28bb 100644 --- a/drivers/perf/riscv_pmu_legacy.c +++ b/drivers/perf/riscv_pmu_legacy.c @@ -13,7 +13,7 @@  #include  #define RISCV_PMU_LEGACY_CYCLE         0 -#define RISCV_PMU_LEGACY_INSTRET       1 +#define RISCV_PMU_LEGACY_INSTRET       2  static bool pmu_init_done; Thanks! > Thanks, > drew > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv