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From:   Andreas Schwab <schwab@suse.de>
To:     Nylon Chen <nylon.chen@sifive.com>
Cc:     Conor Dooley <conor.dooley@microchip.com>,
        linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
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        greentime.hu@sifive.com, zong.li@sifive.com, nylon7717@gmail.com
Subject: Re: [PATCH v2] RISC-V: Support 32_PCREL relocation type in kernel
 module
In-Reply-To: <20230615084310.GA780@hsinchu15> (Nylon Chen's message of "Thu,
        15 Jun 2023 16:43:11 +0800")
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        <CAHh=Yk_=oZJ6eY3jJzLavub5rGsvY=MKv4tGXeiqkz+rgJHwDQ@mail.gmail.com>
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Date:   Thu, 15 Jun 2023 11:11:49 +0200
Message-ID: <mvmo7lh2ip6.fsf@suse.de>
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On Jun 15 2023, Nylon Chen wrote:

> Because LLVM currently has it enabled by default(https://reviews.llvm.org/D145164), it will generate this
> relocation type.
>
>>From what I know, GCC will also enable it in the future.

That's why the kernel explicitly disables it.

-- 
Andreas Schwab, SUSE Labs, schwab@suse.de
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