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Date:   Thu, 15 Jun 2023 13:50:01 +0300
From:   Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To:     "mika.westerberg@linux.intel.com" <mika.westerberg@linux.intel.com>
Cc:     "Jadav, Raag" <raag.jadav@intel.com>,
        "linus.walleij@linaro.org" <linus.walleij@linaro.org>,
        "linux-gpio@vger.kernel.org" <linux-gpio@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "Sangannavar, Mallikarjunappa" 
        <mallikarjunappa.sangannavar@intel.com>,
        "N, Pandith" <pandith.n@intel.com>
Subject: Re: [PATCH v3 2/3] pinctrl: intel: refine ->irq_set_type() hook
Message-ID: <ZIrs2YSEUbPyvZWE@smile.fi.intel.com>
References: <20230613085054.10976-1-raag.jadav@intel.com>
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 <20230615095517.GV45886@black.fi.intel.com>
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Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
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On Thu, Jun 15, 2023 at 12:55:17PM +0300, mika.westerberg@linux.intel.com wrote:
> On Thu, Jun 15, 2023 at 09:48:12AM +0000, Jadav, Raag wrote:
> > > On Tue, Jun 13, 2023 at 02:20:53PM +0530, Raag Jadav wrote:

...

> > > Looking at this I realized that entire temporary variable assignments can be
> > > done outside of spin lock. You probably would need another one for keeping
> > > rxinv value.
> > 
> > Something like this?

Almost, see below.

> >         u32 value, rxevcfg;
> >         u32 rxinv = 0;

No assignment here.

         u32 rxinv, rxevcfg;
         u32 value;

> >         if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
> >                 rxevcfg = PADCFG0_RXEVCFG_EDGE_BOTH;
> >         } else if (type & IRQ_TYPE_EDGE_FALLING) {
> >                 rxevcfg = PADCFG0_RXEVCFG_EDGE;
> >         } else if (type & IRQ_TYPE_EDGE_RISING) {
> >                 rxevcfg = PADCFG0_RXEVCFG_EDGE;
> >         } else if (type & IRQ_TYPE_LEVEL_MASK) {
> >                 rxevcfg = PADCFG0_RXEVCFG_LEVEL;
> >         } else {
> >                 rxevcfg = PADCFG0_RXEVCFG_DISABLED;
> >         }

Now, if it's fully included in the diff (even with --patience parameter),
then you may drop {}.

> >         if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW)
> >                 rxinv = PADCFG0_RXINV;

		else
			rxinv = 0;

> >         raw_spin_lock_irqsave(&pctrl->lock, flags);
> > 
> >         intel_gpio_set_gpio_mode(reg);
> > 
> >         value = readl(reg);
> > 
> >         value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
> >         value |= rxinv;
> >         value |= rxevcfg << PADCFG0_RXEVCFG_SHIFT;

And I would rewrite these to the standard patterns:

         value = (value & ~PADCFG0_RXINV) | rxinv;
         value = (value & ~PADCFG0_RXEVCFG_MASK) | (rxevcfg << PADCFG0_RXEVCFG_SHIFT);

And looking at this, perhaps do shift also outside the lock:

         } else {
                 rxevcfg = PADCFG0_RXEVCFG_DISABLED;
         }
         rxevcfg <<= PADCFG0_RXEVCFG_SHIFT;

But, taking into account scope of the _RXEVCFG_*, I would add shift directly to
the definitions and kill that SHIFT entirely:

#define PADCFG0_RXEVCFG_LEVEL           (0 << 25)
#define PADCFG0_RXEVCFG_EDGE            (1 << 25)
#define PADCFG0_RXEVCFG_DISABLED        (2 << 25)
#define PADCFG0_RXEVCFG_EDGE_BOTH       (3 << 25)

	 ...

         value = (value & ~PADCFG0_RXINV) | rxinv;
         value = (value & ~PADCFG0_RXEVCFG_MASK) | rxevcfg;

Try that one and look if it looks better. It might even save bytes after all.

> >         writel(value, reg);
> 
> This one looks better.
> 
> > > Will it give us any memory reduction in comparison to the current code?
> > 
> > add/remove: 0/0 grow/shrink: 1/0 up/down: 4/0 (4)
> > Function                                     old     new   delta
> > intel_gpio_irq_type                          317     321      +4
> > Total: Before=10469, After=10473, chg +0.04%
> > 
> > Unfortunately gcc doesn't seem to consider this as best of the sequence,
> > and I'm not entirely sure why.
> 
> It's fine as is, readability counts more than few bytes here.

-- 
With Best Regards,
Andy Shevchenko