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Date:   Thu, 15 Jun 2023 14:08:49 +0200
From:   Michael Walle <michael@walle.cc>
To:     Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>
Cc:     tudor.ambarus@linaro.org, pratyush@kernel.org,
        miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com,
        robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
        conor+dt@kernel.org, git@amd.com, linux-mtd@lists.infradead.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        amitrkcian2002@gmail.com
Subject: Re: [PATCH 1/2] dt-bindings: mtd: jedec, spi-nor: Add DT property to
 avoid setting SRWD bit in status register
In-Reply-To: <20230615111649.36344-2-amit.kumar-mahapatra@amd.com>
References: <20230615111649.36344-1-amit.kumar-mahapatra@amd.com>
 <20230615111649.36344-2-amit.kumar-mahapatra@amd.com>
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Am 2023-06-15 13:16, schrieb Amit Kumar Mahapatra:
> If the WP signal of the flash device is not connected and the software 
> sets
> the status register write disable (SRWD) bit in the status register 
> then
> thestatus register permanently becomes read-only. To avoid this added a 
> new
> boolean DT property "broken-wp". If WP signal is not connected, then 
> this
> property should be set in the DT to avoid setting the SRWD during 
> status
> register write operation.
> 
> Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>
> ---
>  .../devicetree/bindings/mtd/jedec,spi-nor.yaml      | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
> b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
> index 89959e5c47ba..a509d34f14b2 100644
> --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
> +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
> @@ -70,6 +70,19 @@ properties:
>        be used on such systems, to denote the absence of a reliable 
> reset
>        mechanism.
> 
> +  broken-wp:
> +    type: boolean
> +    description:
> +      The SRWD bit in status register, combined with the WP signal 
> provides
> +      hardware data protection for the device. When the SRWD bit is 
> set to 1,
> +      and the WP signal is driven LOW, the status register nonvolatile 
> bits
> +      become read-only and the WRITE STATUS REGISTER operation will
> not execute.
> +      The only way to exit this hardware-protected mode is to drive
> WP HIGH. But
> +      if the WP signal of the flash device is not connected then
> status register
> +      permanently becomes read-only as the SRWD bit cannot be reset.
> This boolean
> +      flag can be used on such systems in which WP signal is not 
> connected, to
> +      avoid setting the SRWD bit while writing the status register.

FWIW, this is also a valid use case: have the WP# pin tied to low, the
OEM will program the flash and then enable locking making the flash
permanently write protected. IWO, if the pin is hard strapped to low,
it is not always broken. You might add that to the description.

-michael