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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jun 2023 16:51:19.9104 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1a2b8885-35e0-438b-363a-08db6dc0be7a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A0.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6841 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO,SPF_HELO_PASS, SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org For PCI endpoint defined quirks to generate device tree node, it requires 'ranges' property to translate iomem addresses for its downstream devices. Signed-off-by: Lizhi Hou --- drivers/pci/of_property.c | 33 ++++++++++++++++++++++----------- drivers/pci/quirks.c | 1 + 2 files changed, 23 insertions(+), 11 deletions(-) diff --git a/drivers/pci/of_property.c b/drivers/pci/of_property.c index bdd756c8d7de..08654740f314 100644 --- a/drivers/pci/of_property.c +++ b/drivers/pci/of_property.c @@ -84,15 +84,22 @@ static int of_pci_prop_ranges(struct pci_dev *pdev, struct of_changeset *ocs, struct of_pci_range *rp; struct resource *res; int i = 0, j, ret; + u32 flags, num; u64 val64; - u32 flags; - rp = kcalloc(PCI_BRIDGE_RESOURCE_NUM, sizeof(*rp), GFP_KERNEL); + if (pci_is_bridge(pdev)) { + num = PCI_BRIDGE_RESOURCE_NUM; + res = &pdev->resource[PCI_BRIDGE_RESOURCES]; + } else { + num = PCI_STD_NUM_BARS; + res = &pdev->resource[PCI_STD_RESOURCES]; + } + + rp = kcalloc(num, sizeof(*rp), GFP_KERNEL); if (!rp) return -ENOMEM; - res = &pdev->resource[PCI_BRIDGE_RESOURCES]; - for (j = 0; j < PCI_BRIDGE_RESOURCE_NUM; j++) { + for (j = 0; j < num; j++) { if (!resource_size(&res[j])) continue; @@ -102,8 +109,12 @@ static int of_pci_prop_ranges(struct pci_dev *pdev, struct of_changeset *ocs, val64 = res[j].start; of_pci_set_address(pdev, rp[i].parent_addr, val64, 0, flags, false); - memcpy(rp[i].child_addr, rp[i].parent_addr, - sizeof(rp[i].child_addr)); + if (pci_is_bridge(pdev)) { + memcpy(rp[i].child_addr, rp[i].parent_addr, + sizeof(rp[i].child_addr)); + } else { + rp[i].child_addr[0] = j; + } val64 = resource_size(&res[j]); rp[i].size[0] = upper_32_bits(val64); @@ -161,13 +172,13 @@ int of_pci_add_properties(struct pci_dev *pdev, struct of_changeset *ocs, if (pci_is_bridge(pdev)) { ret |= of_changeset_add_prop_string(ocs, np, "device_type", "pci"); - ret |= of_changeset_add_prop_u32(ocs, np, "#address-cells", - OF_PCI_ADDRESS_CELLS); - ret |= of_changeset_add_prop_u32(ocs, np, "#size-cells", - OF_PCI_SIZE_CELLS); - ret |= of_pci_prop_ranges(pdev, ocs, np); } + ret |= of_pci_prop_ranges(pdev, ocs, np); + ret |= of_changeset_add_prop_u32(ocs, np, "#address-cells", + OF_PCI_ADDRESS_CELLS); + ret |= of_changeset_add_prop_u32(ocs, np, "#size-cells", + OF_PCI_SIZE_CELLS); ret |= of_pci_prop_reg(pdev, ocs, np); ret |= of_pci_prop_compatible(pdev, ocs, np); diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index c8f3acea752d..51945b631628 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -6052,3 +6052,4 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a31, dpc_log_size); */ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5020, of_pci_make_dev_node); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5021, of_pci_make_dev_node); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REDHAT, 0x0005, of_pci_make_dev_node); -- 2.34.1