Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
Message-ID: <da1f680b-f601-0e64-bdb4-1aa5b6fc6175@amd.com>
Date:   Thu, 15 Jun 2023 13:39:41 -0400
User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101
 Thunderbird/102.10.1
Cc:     yazen.ghannam@amd.com, linux-edac@vger.kernel.org,
        linux-kernel@vger.kernel.org, tony.luck@intel.com, x86@kernel.org
Subject: Re: [PATCH] x86/mce: Schedule mce_setup() on correct CPU for CPER
 decoding
Content-Language: en-US
To:     Borislav Petkov <bp@alien8.de>
References: <20230417162006.3292715-1-yazen.ghannam@amd.com>
 <20230615152031.GCZIssPyJjGcikn9iA@fat_crate.local>
 <c9f885df-4650-248c-3708-9250a0b530dc@amd.com>
 <20230615162037.GEZIs6VZG9gVs5QtFT@fat_crate.local>
 <d1333fa6-34e1-8b2a-b772-369776428eae@amd.com>
From:   Yazen Ghannam <yazen.ghannam@amd.com>
In-Reply-To: <d1333fa6-34e1-8b2a-b772-369776428eae@amd.com>
Content-Type: text/plain; charset=UTF-8; format=flowed
Content-Transfer-Encoding: 7bit
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?WXEzTXV6NDVUOTVLM0ZQY3g0Nks3VlJPVnBLY2x0M2svT1czcjBCS0hJbHJa?=
 =?utf-8?B?U29VY2pmWFc0YnhqYmNEakZRMTZESXl4UmM3cGE5MTdqdnF5dWppK055d2hz?=
 =?utf-8?B?eXI4RWxmaUpaNHVRQ3pXNVFYVFhrK1pPNk5Fb0d5TFJNUUZQRE4vYWNjR2t2?=
 =?utf-8?B?MDc5ZktORU5kYzZtTmNhVjNqTnJHRGVGOXg3eDAzd2VhQjhJS1h1Z3V0UFZq?=
 =?utf-8?B?REhENTVPRi85MG1ZL0Npb2NuTVVuWDEzZ1Z0TnAzbEZEejFDL3d2bWJqSnc4?=
 =?utf-8?B?cFVKS1FGa1UwY285WWhiaC9rU2pzU00rL2RxekhpOHllMk1OZFRkeWc3ckVR?=
 =?utf-8?B?czZwRFhHYU5qUm9qakdHZUhLNWNYTmVPOCs2RTI5ZVlvbmxldFNKcWpSY3Fy?=
 =?utf-8?B?Si9mVTFTd1l6bnllVVZ3QkZ3K3VqZGU2QjRNY1NIMmVMdFdtOHBuSStSTWlL?=
 =?utf-8?B?bFJLVTNrTjhzUVFsdm4vdWpYUDVIWUdUZVdkV2NTR3BlOElOVHRsbko1WGZy?=
 =?utf-8?B?Z0Q0S1pjSWVGQWtCV1JBaXZqQVc3MW9LeE1EZWJEQ0xDMkZpSFZMdHZxSmVy?=
 =?utf-8?B?OVc4SUM1VCtnMnNtS2NlaFdoQ21JWjViRlNBNllvQlFPaTRNNUU1cEl4ZEps?=
 =?utf-8?B?WmptMFkyL3hKaEJYeVBUY0ZIQjdtR2VicDh1eG16Slc2LzJrYnpEZ0lWczdT?=
 =?utf-8?B?Q081UWJQVEVRL05tSlAvbGV3WDFjMWRWenl3NkVrM1lXRVNNdnlIQ2dUSzRp?=
 =?utf-8?B?a1lweXhhZEF3ZDgzeUFLTTBKcVJwcGVBa2xEVzM5aTVWMXp2SUdhSndiL3Nj?=
 =?utf-8?B?cGVKWmxFdGw0aXhYMDAzaVVCb1JEMzVCSmlTemwrQ2t3NkxDQys1U3cvNkxI?=
 =?utf-8?B?WUxqUUpiZmYwQTVvT1A4MG1BNDZ2Q2tra1VkMWlLRDRzeHZjWEVQTUM5clhz?=
 =?utf-8?B?eC83eXc0NjVsaHIycHg1dDVFajRMblc0cCtLRUJOYlZYQ2w1amZ0cmVMVVJk?=
 =?utf-8?B?UUZtZnRHV1QwTHFydStlTVdKdVJQOStldVBxakJjTDJ6ZytOZi9FeG90SHht?=
 =?utf-8?B?WEM0S250OHZEQldJV3Rxazd0QkVOWlRsOVhqRlJ1YTJBMGpYbGJ5NGRYbkor?=
 =?utf-8?B?QzdKRFNyWGFsSGEraGozZnlReG9wTEZzSlFlT3BLYUR6N0VMMWZUU01rdTJM?=
 =?utf-8?B?eDlMY05FYmRnYzJnK3MzUzFWMEJsSDhKU3E1aWhjaXFlaVRNWE5iNGxjS0xl?=
 =?utf-8?B?UHdSOW9zL3ZGdUdwd3h1UmJ0Zm55OExWNXgwVmo2VVg5c0FxY3c0WCszSHVH?=
 =?utf-8?B?d2Q5SjlEREswcnRFR2R5TittMWM3MTBqSXVjU3djWEhsZFF6RGFLQ2VtbVBs?=
 =?utf-8?B?Y2tCajZkbExxbXd6ZHVwMFVXREJNNnBCaWhydmJHc0tlTFlUdXVoUDRoTk56?=
 =?utf-8?B?Y0VaN3JvTXI0UUFyR2dsOXB6eW4xNFBsQ0g4NXZuNjhiMWJRczFhQmpPaE5n?=
 =?utf-8?B?SjQ0dVQ2Z1pXME5wTU51ZkJlckxab3R1dGhtNXhlSXZDdmkyd1VkTHZiZHZB?=
 =?utf-8?B?dkVkRFM5SU9ISzBCNWltWlg2OTJiRHUyV1lpYUU4b0gvbnBMQmRtZU9ad3ZD?=
 =?utf-8?B?aWtFL2ZneWFJMXQ2YnoxdkZ0aWNqa1F4eVdjN2ZjMExCVVo3YkFBdkpSekFn?=
 =?utf-8?B?TzRUTVBRRExlQWJLeS9XMVdOOHJacnAwUUF4b0hiWkMvQ0tpaHk1enZub01i?=
 =?utf-8?B?cDRCMW80S05iRjZoNDFmamF5cWhNdlZkRjNXN2Y3a0dYcWZjdGVHd0tRL3Ri?=
 =?utf-8?B?L1Avell1SW1VbnpRQXRvbkJkR0JWUFIxY0YyL0g4ZXJ2VG81eDRyUlVIYlNP?=
 =?utf-8?B?bWJOUW1EWnk2Nyt4TzFuNXBxUGx5M1gwY3dYTW9qaDN0eGlaUnhqYSt3azNp?=
 =?utf-8?B?dW1xbDR5aFZFZi9QMk11MDQvTGdaYW50YitQV29LamEwdjUwOC9qdEhyUk1j?=
 =?utf-8?B?MzFXenoyZUcvWVZONTJZZ0svTW9DanJDRkp1MHFVTzZqYjJEbjVYUHBhY016?=
 =?utf-8?B?NklidmhERzZWMklEbTRobnBJRFMrOU5xbHV6ZFdtbUU2V3NiVlpmQmYvY2ZN?=
 =?utf-8?Q?Lrz25bvCt+J93cEGC+nFXJ6py?=
X-OriginatorOrg: amd.com
X-MS-Exchange-CrossTenant-Network-Message-Id: 8d916cc9-890b-479e-01ea-08db6dc78253
X-MS-Exchange-CrossTenant-AuthSource: BYAPR12MB3109.namprd12.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jun 2023 17:39:45.7231
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: YAdScUs4kpZgX+4KxYsvglkXBabT+19kvkudb3K3R3DixJLhjsViMSj0xUw9Q4EELqSPI95btS0wOdShZMCUtQ==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8237
X-Spam-Status: No, score=-1.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,
        DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO,NICE_REPLY_A,
        RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,
        T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6
X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on
        lindbergh.monkeyblade.net
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

On 6/15/2023 1:02 PM, Yazen Ghannam wrote:
> On 6/15/2023 12:20 PM, Borislav Petkov wrote:
>> On Thu, Jun 15, 2023 at 11:34:21AM -0400, Yazen Ghannam wrote:
>>> We can solve the NMI issue if it ever comes up in the future. Unless 
>>> there's
>>> an obvious change to avoid this now. Any suggestions?
>>
>> Yes, solve it right from the get-go. "It cannot happen now" is not good
>> enough. It should not be even technically possible.
>>
> 
> Okay, understood.
> 
>> Just report what's logged into BERT - nothing more. Whoever needs the
>> remaining info, can dump it from the machine.
>>
> 
> Will do.
> 

How about these changes? I can split this into separate preemption and 
PPIN patches.

The PPIN isn't coming directly from BERT. But it seems we can use the 
per_cpu value which is set up during CPU init.

Thanks,
Yazen

diff --git a/arch/x86/kernel/cpu/mce/apei.c b/arch/x86/kernel/cpu/mce/apei.c
index 8ed341714686..db16dc3c7b03 100644
--- a/arch/x86/kernel/cpu/mce/apei.c
+++ b/arch/x86/kernel/cpu/mce/apei.c
@@ -97,15 +97,19 @@ int apei_smca_report_x86_error(struct 
cper_ia_proc_ctx *ctx_info, u64 lapic_id)
         if (ctx_info->reg_arr_size < 48)
                 return -EINVAL;

+       get_cpu();
         mce_setup(&m);
+       put_cpu();

         m.extcpu = -1;
         m.socketid = -1;
+       m.ppin = 0;

         for_each_possible_cpu(cpu) {
                 if (cpu_data(cpu).initial_apicid == lapic_id) {
                         m.extcpu = cpu;
                         m.socketid = cpu_data(m.extcpu).phys_proc_id;
+                       m.ppin = cpu_data(m.extcpu).ppin;
                         break;
                 }
         }