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Date:   Thu, 15 Jun 2023 20:13:01 +0100
From:   Conor Dooley <conor@kernel.org>
To:     Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>
Cc:     tudor.ambarus@linaro.org, pratyush@kernel.org,
        miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com,
        robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
        conor+dt@kernel.org, git@amd.com, michael@walle.cc,
        linux-mtd@lists.infradead.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, amitrkcian2002@gmail.com
Subject: Re: [PATCH 1/2] dt-bindings: mtd: jedec, spi-nor: Add DT property to
 avoid setting SRWD bit in status register
Message-ID: <20230615-bright-divided-2eb72872d7cc@spud>
References: <20230615111649.36344-1-amit.kumar-mahapatra@amd.com>
 <20230615111649.36344-2-amit.kumar-mahapatra@amd.com>
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On Thu, Jun 15, 2023 at 04:46:48PM +0530, Amit Kumar Mahapatra wrote:
> If the WP signal of the flash device is not connected and the software se=
ts
> the status register write disable (SRWD) bit in the status register then
> thestatus register permanently becomes read-only. To avoid this added a n=
ew
> boolean DT property "broken-wp". If WP signal is not connected, then this
> property should be set in the DT to avoid setting the SRWD during status
> register write operation.
>=20
> Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>
> ---
>  .../devicetree/bindings/mtd/jedec,spi-nor.yaml      | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
>=20
> diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml b/D=
ocumentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
> index 89959e5c47ba..a509d34f14b2 100644
> --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
> +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
> @@ -70,6 +70,19 @@ properties:
>        be used on such systems, to denote the absence of a reliable reset
>        mechanism.
> =20
> +  broken-wp:
> +    type: boolean
> +    description:
> +      The SRWD bit in status register, combined with the WP signal provi=
des

Should the first use of SRWD be spelt out as you did in your commit
message?

> +      The SRWD bit in status register, combined with the WP signal provi=
des
                                                                     ^
nit: missing a comma here I think.

> +      hardware data protection for the device. When the SRWD bit is set =
to 1,
> +      and the WP signal is driven LOW, the status register nonvolatile b=
its
> +      become read-only and the WRITE STATUS REGISTER operation will not =
execute.
> +      The only way to exit this hardware-protected mode is to drive WP H=
IGH. But
> +      if the WP signal of the flash device is not connected then status =
register
> +      permanently becomes read-only as the SRWD bit cannot be reset. Thi=
s boolean
> +      flag can be used on such systems in which WP signal is not connect=
ed, to

nit: s/such//

Otherwise, seems reasonable to me & the detail in the description is
nice.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Cheers,
Conor.

> +      avoid setting the SRWD bit while writing the status register.
> +
>    reset-gpios:
>      description:
>        A GPIO line connected to the RESET (active low) signal of the devi=
ce.
> --=20
> 2.17.1
>=20

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