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baolu.lu@linux.intel.com; joro@8bytes.org; >> will@kernel.org; robin.murphy@arm.com >> Cc: iommu@lists.linux.dev; linux-kernel@vger.kernel.org; Xu, Yanfei >> >> Subject: [PATCH] iommu/vt-d: Fix to flush cache of PASID directory table >> >> Even the PCI devices don't support pasid capability, PASID table is mandatory >> for a PCI device in scalable mode. However flushing cache of pasid directory >> table for these devices are not taken after pasid table is allocated as the "size" >> of table is zero. Fix to assign it with a page size. >> >> Fixes: 194b3348bdbb ("iommu/vt-d: Fix PASID directory pointer coherency") >> Signed-off-by: Yanfei Xu >> --- >> drivers/iommu/intel/pasid.c | 4 +++- >> 1 file changed, 3 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c index >> c5d479770e12..bde7df055865 100644 >> --- a/drivers/iommu/intel/pasid.c >> +++ b/drivers/iommu/intel/pasid.c >> @@ -115,7 +115,9 @@ int intel_pasid_alloc_table(struct device *dev) >> intel_pasid_max_id); >> >> size = max_pasid >> (PASID_PDE_SHIFT - 3); >> - order = size ? get_order(size) : 0; >> + if (!size) >> + size = PAGE_SIZE; > How about merging the logic of the above few lines into this one: > size = info->pasid_supported ? max_pasid >> (PASID_PDE_SHIFT - 3) : PAGE_SIZE; Yes, it would be more intuitive. But the prerequisite is if we can make sure that the value of max_pasid shifted is still greater than 0. I roughly went through the PCIE spec and didn't find out where defines the smallest PASID value for the PCIE device. Thanks, Yanfei > Though the logic is about the same, the suggested one seems more intuitive. > > Regards, > -Tina > >> + order = get_order(size); >> pages = alloc_pages_node(info->iommu->node, >> GFP_KERNEL | __GFP_ZERO, order); >> if (!pages) { >> -- >> 2.34.1 >>