Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
MIME-Version: 1.0
Date:   Fri, 16 Jun 2023 11:51:27 +0200
From:   Michael Walle <michael@walle.cc>
To:     Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>
Cc:     tudor.ambarus@linaro.org, pratyush@kernel.org,
        miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com,
        robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
        conor+dt@kernel.org, git@amd.com, linux-mtd@lists.infradead.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        amitrkcian2002@gmail.com
Subject: Re: [PATCH v2 1/2] dt-bindings: mtd: jedec, spi-nor: Add DT property
 to avoid setting SRWD bit in status register
In-Reply-To: <20230616085513.17632-2-amit.kumar-mahapatra@amd.com>
References: <20230616085513.17632-1-amit.kumar-mahapatra@amd.com>
 <20230616085513.17632-2-amit.kumar-mahapatra@amd.com>
User-Agent: Roundcube Webmail/1.4.13
Message-ID: <f1d065e98d7b0d115e6a2a562a2a5c68@walle.cc>
Content-Type: text/plain; charset=US-ASCII;
 format=flowed
Content-Transfer-Encoding: 7bit
Precedence: bulk

Am 2023-06-16 10:55, schrieb Amit Kumar Mahapatra:
> If the WP signal of the flash device is not connected and the software 
> sets
> the status register write disable (SRWD) bit in the status register 
> then
> thestatus register permanently becomes read-only. To avoid this added a 
> new
> boolean DT property "broken-wp". If WP signal is not connected, then 
> this
> property should be set in the DT to avoid setting the SRWD during 
> status
> register write operation.
> 
> Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  .../devicetree/bindings/mtd/jedec,spi-nor.yaml    | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
> b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
> index 89959e5c47ba..10a6df752f6f 100644
> --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
> +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
> @@ -70,6 +70,21 @@ properties:
>        be used on such systems, to denote the absence of a reliable 
> reset
>        mechanism.
> 
> +  broken-wp:
> +    type: boolean
> +    description:
> +      The status register write disable (SRWD) bit in status register, 
> combined
> +      with the WP signal, provides hardware data protection for the
> device. When
> +      the SRWD bit is set to 1, and the WP signal is either driven LOW 
> or hard
> +      strapped to LOW, the status register nonvolatile bits become
> read-only and
> +      the WRITE STATUS REGISTER operation will not execute. The only
> way to exit
> +      this hardware-protected mode is to drive WP HIGH. If the WP 
> signal of the
> +      flash device is not connected then status register permanently 
> becomes
> +      read-only as the SRWD bit cannot be reset. This boolean flag can 
> be used
> +      on systems in which WP signal is not connected, to avoid setting 
> the SRWD
> +      bit while writing the status register.

This is not true for all flashes, for example, Macronix flashes seem to 
have
an internal pull-up, so if the pin is unconnected H/W write protection 
is
disabled.

So maybe only mention that "if the pin is wrongly tied to GND (that 
includes
internal pull-downs) or it is left floating".

Same goes for your comment in the driver code. Sorry for nitpicking, but
I fear some misuse of this property to disable the locking of the status
register.

> If the WP signal is hard strapped
> +      to LOW then it is not broken as it can be a valid use case.
> +

I'm not sure it the bindings use negative notion of pins, because that
signal is usually called WP#.

-michael