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Message-ID: <6a0a9fe7-d08e-4d1d-0085-f854f95c390f@linaro.org>
Date:   Fri, 16 Jun 2023 13:30:57 +0200
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Subject: Re: [RESEND v6 7/8] arm64: dts: qcom: sc7280: Modify LPASS_MCC reg
 region size in the lpass_tlmm node
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To:     Mohammad Rafi Shaik <quic_mohs@quicinc.com>,
        krzysztof.kozlowski+dt@linaro.org, swboyd@chromium.org,
        andersson@kernel.org, broonie@kernel.org, agross@kernel.org
Cc:     robh+dt@kernel.org, linux-arm-msm@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        quic_rohkumar@quicinc.com, srinivas.kandagatla@linaro.org,
        dianders@chromium.org, judyhsiao@chromium.org,
        quic_visr@quicinc.com,
        Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
References: <20230616103534.4031331-1-quic_mohs@quicinc.com>
 <20230616103534.4031331-8-quic_mohs@quicinc.com>
From:   Konrad Dybcio <konrad.dybcio@linaro.org>
In-Reply-To: <20230616103534.4031331-8-quic_mohs@quicinc.com>
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On 16.06.2023 12:35, Mohammad Rafi Shaik wrote:
> From: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
> 
> Modify LPASS_MCC register region size in "lpass_tlmm" node.
> The pincntl driver requires access until slew-rate register region
> and remaining register region related to the lpass_efuse register
> is not required in pincntl driver as lpass_efuse register region is
> required in adsp remoteproc driver.
> 
> Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
> Signed-off-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com>
> ---
Fixes tag?

Konrad
>  arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 36f9edabb9d7..ec38f2feb9bf 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -2509,7 +2509,7 @@ lpass_ag_noc: interconnect@3c40000 {
>  		lpass_tlmm: pinctrl@33c0000 {
>  			compatible = "qcom,sc7280-lpass-lpi-pinctrl";
>  			reg = <0 0x033c0000 0x0 0x20000>,
> -				<0 0x03550000 0x0 0x10000>;
> +				<0 0x03550000 0x0 0xa100>;
>  			qcom,adsp-bypass-mode;
>  			gpio-controller;
>  			#gpio-cells = <2>;