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From:   Sergio Paracuellos <sergio.paracuellos@gmail.com>
Date:   Sat, 17 Jun 2023 08:00:39 +0200
Message-ID: <CAMhs-H_sHWu_uFMbjzB2APU=aYv6d4gnXD9xw=ANigTXDjQzzg@mail.gmail.com>
Subject: Re: [PATCH v3 2/9] clk: ralink: add clock and reset driver for MTMIPS SoCs
To:     Shiji Yang <yangshiji66@outlook.com>
Cc:     arinc.unal@arinc9.com, devicetree@vger.kernel.org,
        john@phrozen.org, krzysztof.kozlowski+dt@linaro.org,
        linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-mips@vger.kernel.org, matthias.bgg@gmail.com,
        mturquette@baylibre.com, p.zabel@pengutronix.de,
        robh+dt@kernel.org, sboyd@kernel.org, tsbogend@alpha.franken.de
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On Sat, Jun 17, 2023 at 7:51=E2=80=AFAM Shiji Yang <yangshiji66@outlook.com=
> wrote:
>
> Thank you for your quick reply!
>
> >> >+      {
> >> >+              .compatible =3D "ralink,mt7620a-sysc",
> >> >+              .data =3D &mt7620_clk_data,
> >> >+      },
> >> >+      {
> >> >+              .compatible =3D "ralink,mt7620-sysc",
> >> >+              .data =3D &mt7620_clk_data,
> >> >+      },
> >> >+      {
> >>
> >> I am confused about the difference between `ralink,mt7620-sysc` and
> >> `ralink,mt7620a-sysc`. Do you mean mt7620n?
> >> https://www.mediatek.com/products/home-networking/mt7620n-a
> >
> >There is no real difference. As you can see both of them use the same
> >'mt7620_clk_data' but since both compatible strings already exist
> >somewhere I introduced both of them.
> >arch/mips/boot/dts/ralink
>
> If they are the same, perhaps `mt7620a` also need to be checked in mtmips=
_clk_regs_init().
> Or just remove compatible string of `mt7620a` and update dtsi files?

We are planning to properly port dts files from openWRT into the
mainline kernel and also update the current out of date files which
already exist on tree, so we will take care of this kind of details
then.

>
> >+static void __init mtmips_clk_regs_init(struct device_node *node,
> >+                                      struct mtmips_clk_priv *priv)
> >+{
> >+      u32 t;
> >+
> >+      if (!of_device_is_compatible(node, "ralink,mt7620-sysc"))
> >+              return;
> >+
> >+      /*
> >+       * When the CPU goes into sleep mode, the BUS
> >+       * clock will be too low for USB to function properly.
> >+       * Adjust the busses fractional divider to fix this
> >+       */
> >+      regmap_read(priv->sysc, SYSC_REG_CPU_SYS_CLKCFG, &t);
> >+      t &=3D ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK);
> >+      t |=3D CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL;
> >+      regmap_write(priv->sysc, SYSC_REG_CPU_SYS_CLKCFG, t);
> >+}
> >+
>
> If we choose to update dts file. We can also remove the legacy
> "ralink,rt2880-reset" compatible string by the way.

Ditto.

>
> >+static const struct of_device_id mtmips_clk_of_match[] =3D {
> >+      { .compatible =3D "ralink,rt2880-reset" },
> >+      { .compatible =3D "ralink,rt2880-sysc" },
> >+      { .compatible =3D "ralink,rt3050-sysc" },
> >+      { .compatible =3D "ralink,rt3050-sysc" },
> >+      { .compatible =3D "ralink,rt3352-sysc" },
> >+      { .compatible =3D "ralink,rt3883-sysc" },
> >+      { .compatible =3D "ralink,rt5350-sysc" },
> >+      { .compatible =3D "ralink,mt7620a-sysc" },
> >+      { .compatible =3D "ralink,mt7620-sysc" },
> >+      { .compatible =3D "ralink,mt7628-sysc" },
> >+      { .compatible =3D "ralink,mt7688-sysc" },
> >+      {}
> >+};
>
> Thanks,
>     Shiji Yang

Thanks,
    Sergio Paracuellos