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From:   Conor Dooley <conor@kernel.org>
To:     Thomas Gleixner <tglx@linutronix.de>,
        Marc Zyngier <maz@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Daniel Lezcano <daniel.lezcano@linaro.org>,
        Jisheng Zhang <jszhang@kernel.org>
Cc:     conor@kernel.org, Conor Dooley <conor.dooley@microchip.com>,
        Guo Ren <guoren@kernel.org>, Fu Wei <wefu@redhat.com>,
        linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
        linux-riscv@lists.infradead.org, arnd@arndb.de
Subject: Re: [PATCH v3 0/8] Add Sipeed Lichee Pi 4A RISC-V board support
Date:   Sat, 17 Jun 2023 19:20:43 +0100
Message-Id: <20230617-duress-phantom-3da79e33f204@spud>
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From: Conor Dooley <conor.dooley@microchip.com>

On Sun, 18 Jun 2023 00:15:21 +0800, Jisheng Zhang wrote:
> Sipeed's Lichee Pi 4A development board uses Lichee Module 4A core
> module which is powered by T-HEAD's TH1520 SoC. Add minimal device
> tree files for the core module and the development board.
> 
> Support basic uart/gpio/dmac drivers, so supports booting to a basic
> shell.
> 
> [...]

Applied to riscv-dt-for-next, thanks!

[1/8] dt-bindings: interrupt-controller: Add T-HEAD's TH1520 PLIC
      https://git.kernel.org/conor/c/a04cc7391d88
[2/8] dt-bindings: timer: Add T-HEAD TH1520 clint
      https://git.kernel.org/conor/c/413c24b03f4e
[3/8] dt-bindings: riscv: Add T-HEAD TH1520 board compatibles
      https://git.kernel.org/conor/c/89b0186ab532
[4/8] riscv: Add the T-HEAD SoC family Kconfig option
      https://git.kernel.org/conor/c/da47ce003963
[5/8] riscv: dts: add initial T-HEAD TH1520 SoC device tree
      https://git.kernel.org/conor/c/8e396880a864
[6/8] riscv: dts: thead: add sipeed Lichee Pi 4A board device tree
      https://git.kernel.org/conor/c/5af4cb0c42c5
[7/8] MAINTAINERS: add entry for T-HEAD RISC-V SoC
      https://git.kernel.org/conor/c/1203f584fe66
[8/8] riscv: defconfig: enable T-HEAD SoC
      https://git.kernel.org/conor/c/318afa081204

I'll send it to Arnd as a "RISC-V Devicetrees for v6.5 Part 2" once it
has been in linux-next for a day or two.

Going forward, who is going to pick up the patches and send the PRs to
Arnd? I wrote a document that should be in v6.5 about SoC tree
submaintainer stuff that is worth reading:
https://lore.kernel.org/all/20230606-escapable-stuffed-7ca5033e7741@wendy/

I'll do it if nobody else is willing to, but I don't want to be
responsible for applying patches for all the platforms that pop up,
especially for ones that I don't even have the hardware for ;)

Thanks,
Conor.