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Message-ID: <9e9c9f70-7b02-900f-36b9-27c734c12721@linaro.org>
Date:   Sat, 17 Jun 2023 22:36:42 +0200
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Subject: Re: [PATCH v2 4/4] arm64: dts: freescale: Add support for LX2162 SoM
 & Clearfog Board
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To:     Josua Mayer <josua@solid-run.com>, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Cc:     Shawn Guo <shawnguo@kernel.org>,
        Sascha Hauer <s.hauer@pengutronix.de>,
        Pengutronix Kernel Team <kernel@pengutronix.de>,
        Fabio Estevam <festevam@gmail.com>,
        NXP Linux Team <linux-imx@nxp.com>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>,
        Li Yang <leoyang.li@nxp.com>
References: <20230617134009.23042-1-josua@solid-run.com>
 <20230617134009.23042-5-josua@solid-run.com>
From:   Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
In-Reply-To: <20230617134009.23042-5-josua@solid-run.com>
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Precedence: bulk

On 17/06/2023 15:40, Josua Mayer wrote:
> Add support for the SolidRun LX2162A System on Module (SoM), and the
> Clearfog evaluation board.
> 
> The SoM has few software-controllable features:
> - AR8035 Ethernet PHY
> - eMMC
> - SPI Flash
> - fan controller
> - various eeproms
> 
> The Clearfog evaluation board provides:
> - microSD connector
> - USB-A
> - 2x 10Gbps SFP+
> - 2x 25Gbps SFP+ with a retimer
> - 8x 2.5Gbps RJ45
> - 2x mPCI (assembly option / disables 2xRJ45)
> 
> The 8x RJ45 ports are connected with an 8-port PHY: Marvell 88E2580
> supporting up to 5Gbps, while SoC and magnetics are limited to 2.5Gbps.
> 
> However 2500 speed is untested due to documentation and drivier
> limitations. To avoid confusion the phy nodes have been explicitly
> limited to 1000 for now.
> 
> The PCI nodes are disabled, but explicitly added to mark that this board
> can have pci.
> It is expected that the bootloader will patch the status property
> "okay" and disable 2x RJ45 ports, according to active serdes configuration.
> 
> Signed-off-by: Josua Mayer <josua@solid-run.com>
> ---
> V1 -> V2: reordered "compatible" and "reg" properties
> V1 -> V2: replaced chip-specific DT node names with generic ones
> 
>  arch/arm64/boot/dts/freescale/Makefile        |   1 +
>  .../dts/freescale/fsl-lx2162a-clearfog.dts    | 371 ++++++++++++++++++
>  .../dts/freescale/fsl-lx2162a-sr-som.dtsi     |  75 ++++
>  3 files changed, 447 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
>  create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi
> 
> diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
> index ef7d17aef58f..b4fb5044d1c7 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -34,6 +34,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-honeycomb.dtb
>  dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb
>  dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
>  dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2162a-qds.dtb
> +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2162a-clearfog.dtb
>  

...

> +
> +&fspi {
> +	status = "okay";
> +
> +	flash@0 {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "jedec,spi-nor";
> +		reg = <0>;

Still wrong order of properties. compatible is always first, then reg.

Best regards,
Krzysztof