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From:   niravkumar.l.rabara@intel.com
To:     Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>,
        Niravkumar L Rabara <niravkumar.l.rabara@intel.com>,
        Andrew Lunn <andrew@lunn.ch>,
        Dinh Nguyen <dinguyen@kernel.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        Wen Ping <wen.ping.teh@intel.com>,
        Richard Cochran <richardcochran@gmail.com>,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-clk@vger.kernel.org, netdev@vger.kernel.org,
        Adrian Ng Ho Yin <adrian.ho.yin.ng@intel.com>
Subject: [PATCH 0/4] Add support for Agilex5 SoCFPGA platform
Date:   Sun, 18 Jun 2023 21:22:31 +0800
Message-Id: <20230618132235.728641-1-niravkumar.l.rabara@intel.com>
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From: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>

This patch set introduce the changes required for Agilx5 platform.

patch [1/4] - Introduced compatible string for Agilex5 board
patch [2/4] - Add reset and clock header and yaml file.
patch [3/4] - Add clock driver for Agilex5 platform. This patch depends
on patch 2.
patch [4/4] - Add device tree files, socfpga_agilex5_socdk_swvp.dts is
used for Virtual Platform (SIMICS) and socfpga_agilex5_socdk_nand.dts
is used for NAND Flash based board. This patch depends on patch 3.

Niravkumar L Rabara (4):
  dt-bindings: intel: Add Intel Agilex5 compatible
  dt-bindings: clock: Add Intel Agilex5 clocks and resets
  clk: socfpga: agilex5: Add clock driver for Agilex5 platform
  arm64: dts: agilex5: Add initial support for Intel's Agilex5 SoCFPGA

 .../bindings/arm/intel,socfpga.yaml           |   1 +
 .../bindings/clock/intel,agilex5.yaml         |  42 +
 arch/arm64/boot/dts/intel/Makefile            |   3 +
 .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 641 +++++++++++++
 .../boot/dts/intel/socfpga_agilex5_socdk.dts  | 184 ++++
 .../dts/intel/socfpga_agilex5_socdk_nand.dts  | 131 +++
 .../dts/intel/socfpga_agilex5_socdk_swvp.dts  | 248 ++++++
 drivers/clk/socfpga/Kconfig                   |   4 +-
 drivers/clk/socfpga/Makefile                  |   2 +-
 drivers/clk/socfpga/clk-agilex5.c             | 843 ++++++++++++++++++
 drivers/clk/socfpga/clk-pll-s10.c             |  48 +
 drivers/clk/socfpga/stratix10-clk.h           |   2 +
 include/dt-bindings/clock/agilex5-clock.h     | 100 +++
 .../dt-bindings/reset/altr,rst-mgr-agilex5.h  |  79 ++
 14 files changed, 2325 insertions(+), 3 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/intel,agilex5.yaml
 create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
 create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
 create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts
 create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_swvp.dts
 create mode 100644 drivers/clk/socfpga/clk-agilex5.c
 create mode 100644 include/dt-bindings/clock/agilex5-clock.h
 create mode 100644 include/dt-bindings/reset/altr,rst-mgr-agilex5.h

-- 
2.25.1