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Received: from AM9PR04MB8954.eurprd04.prod.outlook.com (2603:10a6:20b:409::7) by AM9PR04MB8259.eurprd04.prod.outlook.com (2603:10a6:20b:3e4::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6500.36; Mon, 19 Jun 2023 08:42:26 +0000 Received: from AM9PR04MB8954.eurprd04.prod.outlook.com ([fe80::5356:c79f:ef9f:dc29]) by AM9PR04MB8954.eurprd04.prod.outlook.com ([fe80::5356:c79f:ef9f:dc29%4]) with mapi id 15.20.6500.036; Mon, 19 Jun 2023 08:42:29 +0000 Message-ID: <9cba4edd-5eab-5a4e-0c10-753495278f8c@oss.nxp.com> Date: Mon, 19 Jun 2023 11:42:28 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH net-next v1 01/14] net: phy: nxp-c45-tja11xx: fix the PTP interrupt enablig/disabling Content-Language: en-US To: Andrew Lunn Cc: hkallweit1@gmail.com, linux@armlinux.org.uk, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, richardcochran@gmail.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, sebastian.tobuschat@nxp.com, stable@vger.kernel.org References: <20230616135323.98215-1-radu-nicolae.pirea@oss.nxp.com> <20230616135323.98215-2-radu-nicolae.pirea@oss.nxp.com> <5f47ee8c-6a84-4449-9331-1895e4a612d9@lunn.ch> From: "Radu Pirea (OSS)" In-Reply-To: <5f47ee8c-6a84-4449-9331-1895e4a612d9@lunn.ch> Content-Type: text/plain; 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This interrupt, the PTP one, acts as a global switch for all >> PTP irqs. >> >> Fixes: 514def5dd339 ("phy: nxp-c45-tja11xx: add timestamping support") >> CC: stable@vger.kernel.org # 5.15+ >> Signed-off-by: Radu Pirea (NXP OSS) > > Please don't mix fixes and development work in one patchset. Please > post this to applying to net, not net-next. Ok. I will send it to net and apply your suggestions. > >> static int nxp_c45_config_intr(struct phy_device *phydev) >> { >> - if (phydev->interrupts == PHY_INTERRUPT_ENABLED) >> + /* The return value is ignored on purpose. It might be < 0. >> + * 0x807A register is not present on SJA1110 PHYs. >> + */ >> + if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { >> + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, >> + VEND1_PORT_FUNC_IRQ_EN, PTP_IRQS); >> return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, >> VEND1_PHY_IRQ_EN, PHY_IRQ_LINK_EVENT); > > phy_set_bits_mmd() will not return an error if the register does not > exist. There is no such indication for MDIO. This is going to do a > read/modify/write. That read might get 0xffff, or random junk. And > then the write back will be successful. The only time > phy_read()/phy_write return error is when there is a problem within > the bus master, like its clock gets turned off and the transfer times > out. > > So it is good to document you are accessing a register which might not > exist, but there is no need to ignore the return code. > > Andrew -- Radu P.