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From:   "Mahapatra, Amit Kumar" <amit.kumar-mahapatra@amd.com>
To:     Rob Herring <robh@kernel.org>
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Subject: RE: [PATCH v2 1/2] dt-bindings: mtd: jedec, spi-nor: Add DT property
 to avoid setting SRWD bit in status register
Thread-Topic: [PATCH v2 1/2] dt-bindings: mtd: jedec, spi-nor: Add DT property
 to avoid setting SRWD bit in status register
Thread-Index: AQHZoDBTwnyTNgO+qkCGryL+tAH4MK+NjU8AgAR2XwA=
Date:   Mon, 19 Jun 2023 11:49:05 +0000
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References: <20230616085513.17632-1-amit.kumar-mahapatra@amd.com>
 <20230616085513.17632-2-amit.kumar-mahapatra@amd.com>
 <20230616152556.GA440257-robh@kernel.org>
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Hello Rob,

> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: Friday, June 16, 2023 8:56 PM
> To: Mahapatra, Amit Kumar <amit.kumar-mahapatra@amd.com>
> Cc: tudor.ambarus@linaro.org; pratyush@kernel.org;
> miquel.raynal@bootlin.com; richard@nod.at; vigneshr@ti.com;
> krzysztof.kozlowski+dt@linaro.org; conor+dt@kernel.org; git (AMD-Xilinx)
> <git@amd.com>; michael@walle.cc; linux-mtd@lists.infradead.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> amitrkcian2002@gmail.com
> Subject: Re: [PATCH v2 1/2] dt-bindings: mtd: jedec, spi-nor: Add DT prop=
erty
> to avoid setting SRWD bit in status register
>=20
> On Fri, Jun 16, 2023 at 02:25:12PM +0530, Amit Kumar Mahapatra wrote:
> > If the WP signal of the flash device is not connected and the software
> > sets the status register write disable (SRWD) bit in the status
> > register then thestatus register permanently becomes read-only. To
> > avoid this added a new boolean DT property "broken-wp". If WP signal
> > is not connected, then this property should be set in the DT to avoid
> > setting the SRWD during status register write operation.
> >
> > Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>
> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> > ---
> >  .../devicetree/bindings/mtd/jedec,spi-nor.yaml    | 15 +++++++++++++++
> >  1 file changed, 15 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
> > b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
> > index 89959e5c47ba..10a6df752f6f 100644
> > --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
> > +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
> > @@ -70,6 +70,21 @@ properties:
> >        be used on such systems, to denote the absence of a reliable res=
et
> >        mechanism.
> >
> > +  broken-wp:
>=20
> In the tied low case, that's designed behavior rather than broken. The na=
me
> should reflect that.

In that case will it be ok to change it to "no-wp". Please let me know if
you have any other suitable name.

Regards,
Amit
>=20
> > +    type: boolean
> > +    description:
> > +      The status register write disable (SRWD) bit in status register,=
 combined
> > +      with the WP signal, provides hardware data protection for the de=
vice.
> When
> > +      the SRWD bit is set to 1, and the WP signal is either driven LOW=
 or hard
> > +      strapped to LOW, the status register nonvolatile bits become rea=
d-only
> and
> > +      the WRITE STATUS REGISTER operation will not execute. The only w=
ay
> to exit
> > +      this hardware-protected mode is to drive WP HIGH. If the WP sign=
al of
> the
> > +      flash device is not connected then status register permanently b=
ecomes
> > +      read-only as the SRWD bit cannot be reset. This boolean flag can=
 be
> used
> > +      on systems in which WP signal is not connected, to avoid setting=
 the
> SRWD
> > +      bit while writing the status register. If the WP signal is hard =
strapped
> > +      to LOW then it is not broken as it can be a valid use case.
> > +
> >    reset-gpios:
> >      description:
> >        A GPIO line connected to the RESET (active low) signal of the de=
vice.
> > --
> > 2.17.1
> >