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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SJ0PR12MB5676.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 57220dd0-3051-4816-fd5b-08db7150b8f3 X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Jun 2023 05:39:31.7067 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: SZzX2vXY+r8ahbLEx2qOJ3YV/sfhRT50lI+e7oM98y4WKeHLh3cxoWJCQdgv5fRzmGUhHRMQtKTfHWJkQ4QvGA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6745 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > -----Original Message----- > From: Ilkka Koskinen > Sent: Wednesday, June 7, 2023 3:32 PM > To: Jonathan Corbet ; Will Deacon ; Mark > Rutland ; Besar Wicaksono > ; Suzuki K Poulose ; > Robin Murphy > Cc: linux-doc@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm- > kernel@lists.infradead.org; Ilkka Koskinen > Subject: [PATCH v3 2/4] perf: arm_cspmu: Support implementation specific > filters >=20 > External email: Use caution opening links or attachments >=20 >=20 > Generic filters aren't used in all the platforms. Instead, the platforms > may use different means to filter events. Add support for implementation > specific filters. >=20 > Signed-off-by: Ilkka Koskinen Reviewed-by: Besar Wicaksono > --- > drivers/perf/arm_cspmu/arm_cspmu.c | 8 ++++++-- > drivers/perf/arm_cspmu/arm_cspmu.h | 4 ++++ > 2 files changed, 10 insertions(+), 2 deletions(-) >=20 > diff --git a/drivers/perf/arm_cspmu/arm_cspmu.c > b/drivers/perf/arm_cspmu/arm_cspmu.c > index f8b4a149eb88..72ca4f56347c 100644 > --- a/drivers/perf/arm_cspmu/arm_cspmu.c > +++ b/drivers/perf/arm_cspmu/arm_cspmu.c > @@ -122,6 +122,9 @@ >=20 > static unsigned long arm_cspmu_cpuhp_state; >=20 > +static void arm_cspmu_set_ev_filter(struct arm_cspmu *cspmu, > + struct hw_perf_event *hwc, u32 filter= ); > + > /* > * In CoreSight PMU architecture, all of the MMIO registers are 32-bit e= xcept > * counter register. The counter register can be implemented as 32-bit o= r 64- > bit > @@ -432,6 +435,7 @@ static int arm_cspmu_init_impl_ops(struct > arm_cspmu *cspmu) > CHECK_DEFAULT_IMPL_OPS(impl_ops, event_type); > CHECK_DEFAULT_IMPL_OPS(impl_ops, event_filter); > CHECK_DEFAULT_IMPL_OPS(impl_ops, event_attr_is_visible); > + CHECK_DEFAULT_IMPL_OPS(impl_ops, set_ev_filter); >=20 > return 0; > } > @@ -798,7 +802,7 @@ static inline void arm_cspmu_set_event(struct > arm_cspmu *cspmu, > writel(hwc->config, cspmu->base0 + offset); > } >=20 > -static inline void arm_cspmu_set_ev_filter(struct arm_cspmu *cspmu, > +static void arm_cspmu_set_ev_filter(struct arm_cspmu *cspmu, > struct hw_perf_event *hwc, > u32 filter) > { > @@ -832,7 +836,7 @@ static void arm_cspmu_start(struct perf_event > *event, int pmu_flags) > arm_cspmu_set_cc_filter(cspmu, filter); > } else { > arm_cspmu_set_event(cspmu, hwc); > - arm_cspmu_set_ev_filter(cspmu, hwc, filter); > + cspmu->impl.ops.set_ev_filter(cspmu, hwc, filter); > } >=20 > hwc->state =3D 0; > diff --git a/drivers/perf/arm_cspmu/arm_cspmu.h > b/drivers/perf/arm_cspmu/arm_cspmu.h > index 51323b175a4a..f89ae2077164 100644 > --- a/drivers/perf/arm_cspmu/arm_cspmu.h > +++ b/drivers/perf/arm_cspmu/arm_cspmu.h > @@ -102,6 +102,10 @@ struct arm_cspmu_impl_ops { > u32 (*event_type)(const struct perf_event *event); > /* Decode filter value from configs */ > u32 (*event_filter)(const struct perf_event *event); > + /* Set event filter */ > + void (*set_ev_filter)(struct arm_cspmu *cspmu, > + struct hw_perf_event *hwc, > + u32 filter); > /* Hide/show unsupported events */ > umode_t (*event_attr_is_visible)(struct kobject *kobj, > struct attribute *attr, int unus= ed); > -- > 2.40.1