Received: by 2002:a05:6358:3188:b0:123:57c1:9b43 with SMTP id q8csp7422161rwd; Tue, 20 Jun 2023 00:40:27 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6HlfWXEX3s7T2hvDnhq/Wsqus8avnuCIe8vVGJ9Vg8qbddCNbFjpMn/TCF4psuoYTU0ugb X-Received: by 2002:a05:6214:f01:b0:625:87e4:1689 with SMTP id gw1-20020a0562140f0100b0062587e41689mr15712405qvb.20.1687246826993; Tue, 20 Jun 2023 00:40:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687246826; cv=none; d=google.com; s=arc-20160816; b=HzNEN034v1NooUgNMYPQhmEplXQbLWlkXB8ABgkLL/w9VSpPb9mrKDSrpP3l0JE23U bxWPGZZikNzIh9DDZkZW3n7DvCwwlKLm2GA7iFHFkatBRyNmaJzKNhQ2qbaqBdnRVl9p eChLtYSfrBY9ZopFhXqs8iZLuUU0PeoTAHGgm+u+/sf9cyBMfWqOK7Ln82vzv0qYYFKS wENmwHK4MXu5835qlVcU/tnbBEMWIEJk5gVDtQCVHyoiN1AEpSbXLY2TCY6Wp2JSdr6+ KZ8lWBqRotOfdJC1OGcBtMFeVqrfzPAgEAScLZZ5uInvYkERspIix++pFsL84c8QZfFC f4SA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=DfyZCmPJgINc2vFaG8QlV7pWGi3oWtmNllEgbtOpkTY=; b=oUB+zB39m8c0AQca5mAY110ZD5hAE4h5JJv3eDUFRkHIbC6JYP89suKIHXbiHFmsgU 2IrhAMBMIURkomCeHgVW9zmqis0dIn3vTMW/kXLvyxh9x9ETTD1V33pNAHISk5KSGaPI 1gWm2OnMlGjwkdW+xB7utRPLXaMEgMfrUds0I3ibi1NeGG0KB+KZd2jJVvYI/kz8reJr CgtolCF419BzAvmVt4vq4Sbyq4TxUd9hIIZDWXuphU2z+/gG+r2YzuBFcC5UUNjzdYzJ vqImPcdS0mBR0giprNNHJZUAdEwphbMJpSqXArPwFsFR2YTf2z1alqpTFofNBlmi2bG6 B/pw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=Iyq2XA8Q; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id p27-20020a637f5b000000b00528ca427963si1154819pgn.709.2023.06.20.00.40.11; Tue, 20 Jun 2023 00:40:26 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=Iyq2XA8Q; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231187AbjFTHem (ORCPT + 99 others); Tue, 20 Jun 2023 03:34:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36750 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229976AbjFTHe1 (ORCPT ); Tue, 20 Jun 2023 03:34:27 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4A33A139; Tue, 20 Jun 2023 00:34:25 -0700 (PDT) Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 35K5xV5p016297; Tue, 20 Jun 2023 07:34:06 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=DfyZCmPJgINc2vFaG8QlV7pWGi3oWtmNllEgbtOpkTY=; b=Iyq2XA8QtDkVThFZlVGB5S4xqj+qE64BgpIRQFMCz4S08p3VAZxDIQRxTG4ulCrcJkRr C8GoDCeO3lD4y06Kwo6YG64SDMXCRI52TJRQLffFoSscbZtDKBHyeSh6xKiL2VRrlh+J z+U2QpYWDPdQX2xRcXB/0ItgOTtgi5ZkFsggri7chrdOAbPAWZAYO9hWDM94/1G+GjbT 7LPHwANQ4UaGgqTngP8Zko8C5oa3UM6PXEHuB9+m98C8RybvSUl6TnDM3vRR5Gb/zV0Q xidhY6UvlFWfgQO+83PJ4tPhZHczz+SU0N+NWpHttvWUDX74NA78hdHqaAl10ongM/Kq 2Q== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3rb3fhrd2b-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 20 Jun 2023 07:34:06 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 35K7Y4Ew025835 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 20 Jun 2023 07:34:04 GMT Received: from taozha-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Tue, 20 Jun 2023 00:33:38 -0700 From: Tao Zhang To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin , Konrad Dybcio , Mike Leach , Rob Herring , Krzysztof Kozlowski CC: Tao Zhang , Jinlong Mao , Leo Yan , Greg Kroah-Hartman , , , , , Tingwei Zhang , Yuanfang Zhang , Trilok Soni , Hao Zhang , , Subject: [PATCH v6 07/13] coresight-tpdm: Add nodes to set trigger timestamp and type Date: Tue, 20 Jun 2023 15:32:35 +0800 Message-ID: <1687246361-23607-8-git-send-email-quic_taozha@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1687246361-23607-1-git-send-email-quic_taozha@quicinc.com> References: <1687246361-23607-1-git-send-email-quic_taozha@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 1lDUvVoPB8hxz1-KFm1CLmVVnMi_5UAi X-Proofpoint-ORIG-GUID: 1lDUvVoPB8hxz1-KFm1CLmVVnMi_5UAi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-06-20_04,2023-06-16_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 clxscore=1015 impostorscore=0 adultscore=0 suspectscore=0 malwarescore=0 lowpriorityscore=0 phishscore=0 mlxscore=0 mlxlogscore=999 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306200067 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The nodes are needed to set or show the trigger timestamp and trigger type. This change is to add these nodes to achieve these function. Signed-off-by: Tao Zhang --- .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 24 ++++++ drivers/hwtracing/coresight/coresight-tpdm.c | 94 ++++++++++++++++++++++ 2 files changed, 118 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index dbc2fbd0..0b7b4ad 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -21,3 +21,27 @@ Description: Accepts only one value - 1. 1 : Reset the dataset of the tpdm + +What: /sys/bus/coresight/devices//dsb_trig_type +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Description: + (Write) Set the trigger type of DSB tpdm. Read the trigger + type of DSB tpdm. + + Accepts only one of the 2 values - 0 or 1. + 0 : Set the DSB trigger type to false + 1 : Set the DSB trigger type to true + +What: /sys/bus/coresight/devices//dsb_trig_ts +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Description: + (Write) Set the trigger timestamp of DSB tpdm. Read the + trigger timestamp of DSB tpdm. + + Accepts only one of the 2 values - 0 or 1. + 0 : Set the DSB trigger type to false + 1 : Set the DSB trigger type to true diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index acc3eea..62efc18 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -20,6 +20,18 @@ DEFINE_CORESIGHT_DEVLIST(tpdm_devs, "tpdm"); +static umode_t tpdm_dsb_is_visible(struct kobject *kobj, + struct attribute *attr, int n) +{ + struct device *dev = kobj_to_dev(kobj); + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (drvdata && (drvdata->datasets & TPDM_PIDR0_DS_DSB)) + return attr->mode; + + return 0; +} + static void tpdm_reset_datasets(struct tpdm_drvdata *drvdata) { if (drvdata->datasets & TPDM_PIDR0_DS_DSB) { @@ -229,8 +241,90 @@ static struct attribute_group tpdm_attr_grp = { .attrs = tpdm_attrs, }; +static ssize_t dsb_trig_type_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + return sysfs_emit(buf, "%u\n", + (unsigned int)drvdata->dsb->trig_type); +} + +/* + * Trigger type (boolean): + * false - Disable trigger type. + * true - Enable trigger type. + */ +static ssize_t dsb_trig_type_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val; + + if ((kstrtoul(buf, 0, &val)) || (val & ~1UL)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + if (val) + drvdata->dsb->trig_type = true; + else + drvdata->dsb->trig_type = false; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(dsb_trig_type); + +static ssize_t dsb_trig_ts_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + return sysfs_emit(buf, "%u\n", + (unsigned int)drvdata->dsb->trig_ts); +} + +/* + * Trigger timestamp (boolean): + * false - Disable trigger timestamp. + * true - Enable trigger timestamp. + */ +static ssize_t dsb_trig_ts_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val; + + if ((kstrtoul(buf, 0, &val)) || (val & ~1UL)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + if (val) + drvdata->dsb->trig_ts = true; + else + drvdata->dsb->trig_ts = false; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(dsb_trig_ts); + +static struct attribute *tpdm_dsb_attrs[] = { + &dev_attr_dsb_trig_ts.attr, + &dev_attr_dsb_trig_type.attr, + NULL, +}; + +static struct attribute_group tpdm_dsb_attr_grp = { + .attrs = tpdm_dsb_attrs, + .is_visible = tpdm_dsb_is_visible, +}; + static const struct attribute_group *tpdm_attr_grps[] = { &tpdm_attr_grp, + &tpdm_dsb_attr_grp, NULL, }; -- 2.7.4