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Date:   Tue, 20 Jun 2023 10:48:52 -0600
From:   Rob Herring <robh@kernel.org>
To:     Conor Dooley <conor@kernel.org>
Cc:     linux-kernel@vger.kernel.org,
        Paul Walmsley <paul.walmsley@sifive.com>,
        linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
        palmer@dabbelt.com, Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor.dooley@microchip.com>
Subject: Re: [PATCH v2 1/2] dt-bindings: riscv: cpus: add a ref the common
 cpu schema
Message-ID: <168727973145.3803765.17862726534015699285.robh@kernel.org>
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 <20230615-dubiously-parasail-79d34cefedce@spud>
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On Thu, 15 Jun 2023 23:50:14 +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> To permit validation of RISC-V cpu nodes, "additionalProperties: true"
> needs to be swapped for "unevaluatedProperties: false". To facilitate
> this in a way that passes dt_binding_check, a reference to the cpu
> schema is required.
> 
> Disallow the generic cache-op-block-size property that that drags in,
> since the RISC-V CBO extensions do not require a common size, and have
> individual properties.
> 
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++
>  1 file changed, 6 insertions(+)
> 

Reviewed-by: Rob Herring <robh@kernel.org>