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Message-ID: <c30235e8-a7bd-dac4-a42c-ed673991e4ab@rasmusvillemoes.dk>
Date:   Wed, 21 Jun 2023 13:37:00 +0200
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Subject: Re: [PATCH net-next 3/3] net: dsa: microchip: fix writes to phy
 registers >= 0x10
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To:     Andrew Lunn <andrew@lunn.ch>
Cc:     Woojung Huh <woojung.huh@microchip.com>,
        UNGLinuxDriver@microchip.com,
        Florian Fainelli <f.fainelli@gmail.com>,
        Vladimir Oltean <olteanv@gmail.com>,
        "David S. Miller" <davem@davemloft.net>,
        Eric Dumazet <edumazet@google.com>,
        Jakub Kicinski <kuba@kernel.org>,
        Paolo Abeni <pabeni@redhat.com>, netdev@vger.kernel.org,
        linux-kernel@vger.kernel.org
References: <20230620113855.733526-1-linux@rasmusvillemoes.dk>
 <20230620113855.733526-4-linux@rasmusvillemoes.dk>
 <88474092-70cb-40fc-9c01-1fc8527d5bcb@lunn.ch>
From:   Rasmus Villemoes <linux@rasmusvillemoes.dk>
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On 20/06/2023 21.28, Andrew Lunn wrote:
> On Tue, Jun 20, 2023 at 01:38:54PM +0200, Rasmus Villemoes wrote:
>> According to the errata sheets for ksz9477 and ksz9567, writes to the
>> PHY registers 0x10-0x1f (i.e. those located at addresses 0xN120 to
>> 0xN13f) must be done as a 32 bit write to the 4-byte aligned address
>> containing the register, hence requires a RMW in order not to change
>> the adjacent PHY register.
> 
> ASIC engineers do see to come up with novel ways to break things.
> 
> I assume you have not seen real problems with this, which is why it is
> not for net and a Fixes: tag?

Well, not real problems yet, no. The back story is that I want/need to
implement support for "single LED mode" on the ksz9567, because our
board has two separate simple LEDs for link/activity, and not some
multi-color LED that can indicate speed/link/activity. So that means
writing a 1 to bit 4 of MMD reg 2/0, but due to an errata, _also_
writing a 1 to bit 9 of phy register 0x1e, and when one wants to do
that, this errata applies.

Rasmus