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Message-ID: <e76180a1b82d1c29715587e94e2d6923b64bb893.camel@xry111.site>
Subject: Re: A question about prefetchw detection in "x86/asm: Cleanup
 prefetch primitives"
From:   Xi Ruoyao <xry111@xry111.site>
To:     Borislav Petkov <bp@alien8.de>
Cc:     x86@kernel.org, linux-kernel@vger.kernel.org,
        Thomas Gleixner <tglx@linutronix.de>
Date:   Wed, 21 Jun 2023 20:04:39 +0800
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On Wed, 2023-06-21 at 19:18 +0800, Xi Ruoyao wrote:
> On Wed, 2023-06-21 at 13:13 +0200, Borislav Petkov wrote:
> > On Wed, Jun 21, 2023 at 06:57:40PM +0800, Xi Ruoyao wrote:
> > > I intend to implement the same logic for Glibc.=C2=A0 I can understan=
d "3DNow
> > > implies PREFETCHW", but is there a bibliographical reference about "L=
M
> > > implies PREFETCHW" so I can convince the Glibc maintainers for the
> > > change?
> >=20
> > https://www.amd.com/system/files/TechDocs/24594.pdf
>=20
> Thanks very much!

Hmm, while it's true for AMD, the Intel SDM claims otherwise.  It says
prefetchw is only (really) supported with "Intel=C2=AE Core=E2=84=A2 M proc=
essor
family; 5th Generation Intel=C2=AE Core=E2=84=A2 processor family, Intel At=
om
processor based on Silvermont microarchitecture" or later.  On the
earlier Intel CPUs supporting LM, the prefetchw instruction is treated
as NOP.

Is the kernel code an oversight or we simply don't want to bother
checking Intel vs. AMD here?

--=20
Xi Ruoyao <xry111@xry111.site>
School of Aerospace Science and Technology, Xidian University