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Subject: Re: A question about prefetchw detection in "x86/asm: Cleanup
 prefetch primitives"
From:   Xi Ruoyao <xry111@xry111.site>
To:     Borislav Petkov <bp@alien8.de>
Cc:     x86@kernel.org, linux-kernel@vger.kernel.org,
        Thomas Gleixner <tglx@linutronix.de>
Date:   Wed, 21 Jun 2023 21:06:51 +0800
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On Wed, 2023-06-21 at 14:57 +0200, Borislav Petkov wrote:
> On Wed, Jun 21, 2023 at 08:04:39PM +0800, Xi Ruoyao wrote:
> > Hmm, while it's true for AMD, the Intel SDM claims otherwise.=C2=A0 It
> > says
> > prefetchw is only (really) supported with "Intel=C2=AE Core=E2=84=A2 M =
processor
> > family; 5th Generation Intel=C2=AE Core=E2=84=A2 processor family, Inte=
l Atom
> > processor based on Silvermont microarchitecture" or later.=C2=A0 On the
> > earlier Intel CPUs supporting LM, the prefetchw instruction is
> > treated
> > as NOP.
>=20
> And this is a problem because?

I think it's not an issue in the kernel itself, but announcing
3dnowprefetch in /proc/cpuinfo for an old Intel CPU w/o real prefetchw
implementation seems problematic (to me).
>=20

--=20
Xi Ruoyao <xry111@xry111.site>
School of Aerospace Science and Technology, Xidian University