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Wed, 21 Jun 2023 22:55:37 -0500 From: Terry Bowman To: , , , , , , , CC: , , , Subject: [PATCH v6 16/27] cxl/port: Store the downstream port's Component Register mappings in struct cxl_dport Date: Wed, 21 Jun 2023 22:51:15 -0500 Message-ID: <20230622035126.4130151-17-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230622035126.4130151-1-terry.bowman@amd.com> References: <20230622035126.4130151-1-terry.bowman@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT114:EE_|LV3PR12MB9215:EE_ X-MS-Office365-Filtering-Correlation-Id: b128c6b9-36c9-4a30-0f1e-08db72d48b0c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: NyGuUrGhjBqtEh5QZ3REX90mfTadn8E3YGyHIIeo1kP8bTl8nyehAxPM3/qR4+wsqYtIXA/SXfTSX/uNHH3GoFrERtReKqwVgoRNZ9sUSbOG0P1GpAUDf4R+mi6FQfAXV688jonFT3PUB7iaHFnKm4tFbVr47TOzy8Tzin3z9hWfr09z/jk6nVIOfEQPTlXPaLFp6WgxQnp9Q7gAroqskgwEa9hHUGmnZgzg5yAJ6Vq8q6b1vbUsPg+Rry0dSS4i+R+iG654+jXBM1nNcW3Tm1gmkWgOxGnU06lLJig0O45abmV1gDJab99PYJmAnWg21bmvsLV5kX4Zg0UNUY+9LclIQ0ct5bOs9tZfrlGUjGSgDnaNr7h864mCOjQgGHDhxlLjoFII1rTlodxys9H0s/EpBCb5CChQRUvmnYEvJReYGuisDbdiqzMGaSeBmPaQrUgWTZlXVTfg1prEXFNBtc+Ki2UZydKVrMFzd6c5Kbb44PCkV6wXqzkfQaL752WLTzMkkNw4J2QVyHBVVTVJH8GJeM4WbQxVIaKr+sNc814sMEqj47uIi/+1sWhDiRBATtuYreog85xRSGEX3GBOzvgzLj4U2M7zGfi0At1tfEP7p6RZUKFUqii3wEm9G9wKfsw8lKJhmopiHod3j0n/9zN1Y6HLkRnpaJvebdWJ1XfNUJK4vTsJVGMIhpn2XuSTfpPi4t0KqLnEmuky7Cd8MbTuvQde19l+GKfxag2mWsbgjtbnKT4guuh4A847/y7dT37OuUnekAUXhTLivCeFcw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(136003)(346002)(376002)(39860400002)(396003)(451199021)(46966006)(36840700001)(40470700004)(82310400005)(7416002)(44832011)(356005)(86362001)(47076005)(8936002)(41300700001)(5660300002)(316002)(70206006)(70586007)(81166007)(2616005)(336012)(36860700001)(426003)(83380400001)(82740400003)(186003)(16526019)(26005)(40460700003)(1076003)(54906003)(4326008)(6666004)(110136005)(478600001)(2906002)(36756003)(8676002)(40480700001)(7696005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jun 2023 03:55:39.4044 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b128c6b9-36c9-4a30-0f1e-08db72d48b0c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT114.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9215 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO,SPF_HELO_PASS, SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Robert Richter Same as for ports, also store the downstream port's Component Register mappings, use struct cxl_dport for that. Signed-off-by: Robert Richter Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron --- drivers/cxl/core/port.c | 11 +++++++++++ drivers/cxl/cxl.h | 2 ++ 2 files changed, 13 insertions(+) diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 2e239fd33df9..45fe7d89f7f3 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -710,6 +710,13 @@ static inline int cxl_port_setup_regs(struct cxl_port *port, component_reg_phys); } +static inline int cxl_dport_setup_regs(struct cxl_dport *dport, + resource_size_t component_reg_phys) +{ + return cxl_setup_comp_regs(dport->dport_dev, &dport->comp_map, + component_reg_phys); +} + static struct cxl_port *__devm_cxl_add_port(struct device *host, struct device *uport_dev, resource_size_t component_reg_phys, @@ -988,6 +995,10 @@ __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev, dport->port_id = port_id; dport->port = port; + rc = cxl_dport_setup_regs(dport, component_reg_phys); + if (rc) + return ERR_PTR(rc); + cond_cxl_root_lock(port); rc = add_dport(port, dport); cond_cxl_root_unlock(port); diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 37fa5b565362..b1adca9b27ba 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -595,6 +595,7 @@ struct cxl_rcrb_info { /** * struct cxl_dport - CXL downstream port * @dport_dev: PCI bridge or firmware device representing the downstream link + * @comp_map: component register capability mappings * @port_id: unique hardware identifier for dport in decoder target list * @rcrb: Data about the Root Complex Register Block layout * @rch: Indicate whether this dport was enumerated in RCH or VH mode @@ -602,6 +603,7 @@ struct cxl_rcrb_info { */ struct cxl_dport { struct device *dport_dev; + struct cxl_register_map comp_map; int port_id; struct cxl_rcrb_info rcrb; bool rch; -- 2.34.1