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From:   Besar Wicaksono <bwicaksono@nvidia.com>
To:     Ilkka Koskinen <ilkka@os.amperecomputing.com>,
        Will Deacon <will@kernel.org>,
        Robin Murphy <robin.murphy@arm.com>,
        Suzuki K Poulose <suzuki.poulose@arm.com>,
        Mark Rutland <mark.rutland@arm.com>
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        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: RE: [PATCH 1/4] perf: arm_cspmu: Split 64-bit write to 32-bit writes
Thread-Topic: [PATCH 1/4] perf: arm_cspmu: Split 64-bit write to 32-bit writes
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Date:   Thu, 22 Jun 2023 10:17:46 +0000
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 <20230622011141.328029-2-ilkka@os.amperecomputing.com>
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> -----Original Message-----
> From: Ilkka Koskinen <ilkka@os.amperecomputing.com>
> Sent: Thursday, June 22, 2023 8:12 AM
> To: Will Deacon <will@kernel.org>; Robin Murphy <robin.murphy@arm.com>;
> Besar Wicaksono <bwicaksono@nvidia.com>; Suzuki K Poulose
> <suzuki.poulose@arm.com>; Mark Rutland <mark.rutland@arm.com>
> Cc: Ilkka Koskinen <ilkka@os.amperecomputing.com>; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org
> Subject: [PATCH 1/4] perf: arm_cspmu: Split 64-bit write to 32-bit writes
>=20
> External email: Use caution opening links or attachments
>=20
>=20
> Split the 64-bit register accesses if 64-bit access is not supported
> by the PMU.
>=20
> Signed-off-by: Ilkka Koskinen <ilkka@os.amperecomputing.com>

Reviewed-by: Besar Wicaksono <bwicaksono@nvidia.com>

Thanks,
Besar

> ---
>  drivers/perf/arm_cspmu/arm_cspmu.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
>=20
> diff --git a/drivers/perf/arm_cspmu/arm_cspmu.c
> b/drivers/perf/arm_cspmu/arm_cspmu.c
> index e2b7827c4563..0f517152cb4e 100644
> --- a/drivers/perf/arm_cspmu/arm_cspmu.c
> +++ b/drivers/perf/arm_cspmu/arm_cspmu.c
> @@ -696,7 +696,10 @@ static void arm_cspmu_write_counter(struct
> perf_event *event, u64 val)
>         if (use_64b_counter_reg(cspmu)) {
>                 offset =3D counter_offset(sizeof(u64), event->hw.idx);
>=20
> -               writeq(val, cspmu->base1 + offset);
> +               if (cspmu->has_atomic_dword)
> +                       writeq(val, cspmu->base1 + offset);
> +               else
> +                       lo_hi_writeq(val, cspmu->base1 + offset);
>         } else {
>                 offset =3D counter_offset(sizeof(u32), event->hw.idx);
>=20
> --
> 2.40.1