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Date:   Thu, 22 Jun 2023 09:42:01 -0500
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Subject: Re: [PATCH v6 23/27] cxl/pci: Map RCH downstream AER registers for
 logging protocol errors
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To:     Jonathan Cameron <Jonathan.Cameron@Huawei.com>
Cc:     alison.schofield@intel.com, vishal.l.verma@intel.com,
        ira.weiny@intel.com, bwidawsk@kernel.org, dan.j.williams@intel.com,
        dave.jiang@intel.com, linux-cxl@vger.kernel.org, rrichter@amd.com,
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References: <20230622035126.4130151-1-terry.bowman@amd.com>
 <20230622035126.4130151-24-terry.bowman@amd.com>
 <20230622141627.00000383@Huawei.com>
From:   Terry Bowman <Terry.Bowman@amd.com>
In-Reply-To: <20230622141627.00000383@Huawei.com>
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Hi Jonathan,

Thanks for the reviews.

On 6/22/23 08:16, Jonathan Cameron wrote:
> On Wed, 21 Jun 2023 22:51:22 -0500
> Terry Bowman <terry.bowman@amd.com> wrote:
> 
>> The restricted CXL host (RCH) error handler will log protocol errors
>> using AER and RAS status registers. The AER and RAS registers need
>> to be virtually memory mapped before enabling interrupts. Update
>> __devm_cxl_add_dport() to include RCH RAS and AER mapping.
>>
>> Add 'struct cxl_regs' to 'struct cxl_dport' for saving a unique copy of
>> the RCH downstream port's mapped registers.
> 
> Copy of the address at which they are mapped, not the registers.
> Probably worth tweaking description to make that clearer.
> 

Good point. I'll change to the following:

"Add 'struct cxl_regs' to 'struct cxl_dport' for saving a pointer to
the RCH downstream port's AER and RAS registers."

Regards,
Terry