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Message-ID: <f2ca0d67-25e7-1313-9cea-fddb1ad28c9b@quicinc.com>
Date:   Thu, 22 Jun 2023 09:19:08 -0600
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Subject: Re: [PATCH 3/9] clk: qcom: gcc-msm8998: Control MMSS and GPUSS GPLL0
 outputs properly
Content-Language: en-US
To:     Konrad Dybcio <konrad.dybcio@linaro.org>,
        Andy Gross <agross@kernel.org>,
        Bjorn Andersson <andersson@kernel.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>,
        Taniya Das <tdas@codeaurora.org>
CC:     Marijn Suijten <marijn.suijten@somainline.org>,
        <linux-arm-msm@vger.kernel.org>, <linux-clk@vger.kernel.org>,
        <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@collabora.com>,
        Jami Kettunen <jami.kettunen@somainline.org>
References: <20230622-topic-8998clk-v1-0-5b7a0d6e98b1@linaro.org>
 <20230622-topic-8998clk-v1-3-5b7a0d6e98b1@linaro.org>
 <e880bad8-4fcb-97c1-ec9c-9122e1b550e6@quicinc.com>
 <18f508e7-8a7e-162b-4bed-eaef45147a22@linaro.org>
From:   Jeffrey Hugo <quic_jhugo@quicinc.com>
In-Reply-To: <18f508e7-8a7e-162b-4bed-eaef45147a22@linaro.org>
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Precedence: bulk

On 6/22/2023 9:05 AM, Konrad Dybcio wrote:
> On 22.06.2023 16:55, Jeffrey Hugo wrote:
>> On 6/22/2023 5:57 AM, Konrad Dybcio wrote:
>>> Up until now, we've been relying on some non-descript hardware magic
>>> to pinkypromise turn the clocks on for us. While new SoCs shine with
>>> that feature, MSM8998 can not always be fully trusted.
>>>
>>> Register the MMSS and GPUSS GPLL0 legs with the CCF to allow for manual
>>> enable voting.
>>>
>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>>> ---
>>>    drivers/clk/qcom/gcc-msm8998.c | 58 ++++++++++++++++++++++++++++++++++++++++++
>>>    1 file changed, 58 insertions(+)
>>>
>>> diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c
>>> index be024f8093c5..cccb19cae481 100644
>>> --- a/drivers/clk/qcom/gcc-msm8998.c
>>> +++ b/drivers/clk/qcom/gcc-msm8998.c
>>> @@ -25,6 +25,9 @@
>>>    #include "reset.h"
>>>    #include "gdsc.h"
>>>    +#define GCC_MMSS_MISC    0x0902C
>>> +#define GCC_GPU_MISC    0x71028
>>> +
>>>    static struct pll_vco fabia_vco[] = {
>>>        { 250000000, 2000000000, 0 },
>>>        { 125000000, 1000000000, 1 },
>>> @@ -1367,6 +1370,22 @@ static struct clk_branch gcc_boot_rom_ahb_clk = {
>>>        },
>>>    };
>>>    +static struct clk_branch gcc_mmss_gpll0_div_clk = {
>>> +    .halt_check = BRANCH_HALT_DELAY,
>>> +    .clkr = {
>>> +        .enable_reg = 0x5200c,
>>> +        .enable_mask = BIT(0),
>>> +        .hw.init = &(struct clk_init_data){
>>> +            .name = "gcc_mmss_gpll0_div_clk",
>>> +            .parent_hws = (const struct clk_hw *[]) {
>>> +                &gpll0_out_main.clkr.hw,
>>> +            },
>>> +            .num_parents = 1,
>>> +            .ops = &clk_branch2_ops,
>>> +        },
>>> +    },
>>> +};
>>> +
>>>    static struct clk_branch gcc_mmss_gpll0_clk = {
>>>        .halt_check = BRANCH_HALT_DELAY,
>>>        .clkr = {
>>> @@ -1395,6 +1414,38 @@ static struct clk_branch gcc_mss_gpll0_div_clk_src = {
>>>        },
>>>    };
>>>    +static struct clk_branch gcc_gpu_gpll0_div_clk = {
>>> +    .halt_check = BRANCH_HALT_DELAY,
>>> +    .clkr = {
>>> +        .enable_reg = 0x5200c,
>>> +        .enable_mask = BIT(3),
>>> +        .hw.init = &(struct clk_init_data){
>>> +            .name = "gcc_gpu_gpll0_div_clk",
>>> +            .parent_hws = (const struct clk_hw *[]) {
>>> +                &gpll0_out_main.clkr.hw,
>>> +            },
>>> +            .num_parents = 1,
>>> +            .ops = &clk_branch2_ops,
>>> +        },
>>> +    },
>>> +};
>>> +
>>> +static struct clk_branch gcc_gpu_gpll0_clk = {
>>> +    .halt_check = BRANCH_HALT_DELAY,
>>> +    .clkr = {
>>> +        .enable_reg = 0x5200c,
>>> +        .enable_mask = BIT(4),
>>> +        .hw.init = &(struct clk_init_data){
>>> +            .name = "gcc_gpu_gpll0_clk",
>>> +            .parent_hws = (const struct clk_hw *[]) {
>>> +                &gpll0_out_main.clkr.hw,
>>> +            },
>>> +            .num_parents = 1,
>>> +            .ops = &clk_branch2_ops,
>>> +        },
>>> +    },
>>> +};
>>> +
>>>    static struct clk_branch gcc_blsp1_ahb_clk = {
>>>        .halt_reg = 0x17004,
>>>        .halt_check = BRANCH_HALT_VOTED,
>>> @@ -3080,6 +3131,9 @@ static struct clk_regmap *gcc_msm8998_clocks[] = {
>>>        [AGGRE2_SNOC_NORTH_AXI] = &aggre2_snoc_north_axi_clk.clkr,
>>>        [SSC_XO] = &ssc_xo_clk.clkr,
>>>        [SSC_CNOC_AHBS_CLK] = &ssc_cnoc_ahbs_clk.clkr,
>>> +    [GCC_MMSS_GPLL0_DIV_CLK] = &gcc_mmss_gpll0_div_clk.clkr,
>>> +    [GCC_GPU_GPLL0_DIV_CLK] = &gcc_gpu_gpll0_div_clk.clkr,
>>> +    [GCC_GPU_GPLL0_CLK] = &gcc_gpu_gpll0_clk.clkr,
>>>    };
>>>      static struct gdsc *gcc_msm8998_gdscs[] = {
>>> @@ -3235,6 +3289,10 @@ static int gcc_msm8998_probe(struct platform_device *pdev)
>>>        if (ret)
>>>            return ret;
>>>    +    /* Disable the GPLL0 active input to MMSS and GPU via MISC registers */
>>> +    regmap_write(regmap, GCC_MMSS_MISC, 0x10003);
>>> +    regmap_write(regmap, GCC_GPU_MISC, 0x10003);
>>
>> I wonder, does this disrupt a handoff of an active display from the bootloader to Linux?
> My phone's bootloader doesn't initialize the display, if you (or Angelo
> or Jami, +CC) could test this, it'd be wonderful.

Let me carve out some time to try it on the laptop.