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Message-ID: <b990638b-a86a-ee43-f8b1-18a0a0651ad0@rivosinc.com>
Date:   Thu, 22 Jun 2023 11:28:51 -0700
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Subject: Re: [PATCH] riscv: Discard vector state on syscalls
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To:     =?UTF-8?B?QmrDtnJuIFTDtnBlbA==?= <bjorn@kernel.org>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        linux-riscv@lists.infradead.org
Cc:     =?UTF-8?B?QmrDtnJuIFTDtnBlbA==?= <bjorn@rivosinc.com>,
        linux-kernel@vger.kernel.org, linux@rivosinc.com,
        Palmer Dabbelt <palmer@rivosinc.com>,
        =?UTF-8?Q?R=c3=a9mi_Denis-Courmont?= <remi@remlab.net>,
        Darius Rad <darius@bluespec.com>,
        Andy Chiu <andy.chiu@sifive.com>
References: <20230622173613.30722-1-bjorn@kernel.org>
From:   Vineet Gupta <vineetg@rivosinc.com>
In-Reply-To: <20230622173613.30722-1-bjorn@kernel.org>
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On 6/22/23 10:36, Björn Töpel wrote:
> From: Björn Töpel <bjorn@rivosinc.com>
>
> The RISC-V vector specification states:
>    Executing a system call causes all caller-saved vector registers
>    (v0-v31, vl, vtype) and vstart to become unspecified.

So the only use case of saving/restoring V regs in __switch_to is an 
interrupt induced task switch ?

>
> The vector registers are cleared, vill is set (invalid), and the
> vector status is set to Initial.
>
> That way we can prevent userspace from accidentally relying on the
> stated save.
>
> Rémi pointed out [1] that clearing the registers might be superfluous,
> and setting vill is sufficient.
>
> Link: https://lore.kernel.org/linux-riscv/12784326.9UPPK3MAeB@basile.remlab.net/ # [1]
> Suggested-by: Palmer Dabbelt <palmer@rivosinc.com>
> Suggested-by: Rémi Denis-Courmont <remi@remlab.net>
> Signed-off-by: Björn Töpel <bjorn@rivosinc.com>
> ---
>
> I figured I'd sent out a proper patch. I like Andy's optimization
> patch, but TBH I think we should do that as a follow up.
>
> As Rémi pointed out, the clearing might be opted out, but I left it in
> here.
>
>
> Björn
>
> ---
>   arch/riscv/include/asm/vector.h | 25 +++++++++++++++++++++++++
>   arch/riscv/kernel/traps.c       |  2 ++
>   2 files changed, 27 insertions(+)
>
> diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h
> index 04c0b07bf6cd..692ce55e4a69 100644
> --- a/arch/riscv/include/asm/vector.h
> +++ b/arch/riscv/include/asm/vector.h
> @@ -163,6 +163,30 @@ static inline void __switch_to_vector(struct task_struct *prev,
>   void riscv_v_vstate_ctrl_init(struct task_struct *tsk);
>   bool riscv_v_vstate_ctrl_user_allowed(void);
>   
> +static inline void riscv_v_vstate_discard(struct pt_regs *regs)
> +{
> +	unsigned long vl, vtype_inval = 1UL << (BITS_PER_LONG - 1);
> +
> +	if (!riscv_v_vstate_query(regs))
> +		return;
> +
> +	riscv_v_enable();
> +	asm volatile (
> +		".option push\n\t"
> +		".option arch, +v\n\t"
> +		"vsetvli	%0, x0, e8, m8, ta, ma\n\t"
> +		"vmv.v.i	v0, 0\n\t"
> +		"vmv.v.i	v8, 0\n\t"
> +		"vmv.v.i	v16, 0\n\t"
> +		"vmv.v.i	v24, 0\n\t"
> +		"vsetvl		%0, x0, %1\n\t"
> +		".option pop\n\t"
> +		: "=&r" (vl) : "r" (vtype_inval) : "memory");
> +	riscv_v_disable();
> +
> +	riscv_v_vstate_on(regs);
> +}
> +
>   #else /* ! CONFIG_RISCV_ISA_V  */
>   
>   struct pt_regs;
> @@ -178,6 +202,7 @@ static inline bool riscv_v_vstate_ctrl_user_allowed(void) { return false; }
>   #define __switch_to_vector(__prev, __next)	do {} while (0)
>   #define riscv_v_vstate_off(regs)		do {} while (0)
>   #define riscv_v_vstate_on(regs)			do {} while (0)
> +#define riscv_v_vstate_discard(regs)		do {} while (0)
>   
>   #endif /* CONFIG_RISCV_ISA_V */
>   
> diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c
> index 05ffdcd1424e..00c68b57ff88 100644
> --- a/arch/riscv/kernel/traps.c
> +++ b/arch/riscv/kernel/traps.c
> @@ -295,6 +295,8 @@ asmlinkage __visible __trap_section void do_trap_ecall_u(struct pt_regs *regs)
>   		regs->epc += 4;
>   		regs->orig_a0 = regs->a0;
>   
> +		riscv_v_vstate_discard(regs);
> +
>   		syscall = syscall_enter_from_user_mode(regs, syscall);
>   
>   		if (syscall < NR_syscalls)
>
> base-commit: 4681dacadeefa5ca6017e00736adc1d7dc963c6a