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From:   "Pandey, Radhey Shyam" <radhey.shyam.pandey@amd.com>
To:     Maxim Kochetkov <fido_max@inbox.ru>,
        "netdev@vger.kernel.org" <netdev@vger.kernel.org>
CC:     "David S. Miller" <davem@davemloft.net>,
        Eric Dumazet <edumazet@google.com>,
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        <linux-arm-kernel@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: RE: [PATCH v2 1/1] net: axienet: Move reset before DMA detection
Thread-Topic: [PATCH v2 1/1] net: axienet: Move reset before DMA detection
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Date:   Thu, 22 Jun 2023 18:43:02 +0000
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> -----Original Message-----
> From: Maxim Kochetkov <fido_max@inbox.ru>
> Sent: Thursday, June 22, 2023 11:22 PM
> To: netdev@vger.kernel.org
> Cc: Maxim Kochetkov <fido_max@inbox.ru>; Pandey, Radhey Shyam
> <radhey.shyam.pandey@amd.com>; David S. Miller
> <davem@davemloft.net>; Eric Dumazet <edumazet@google.com>; Jakub
> Kicinski <kuba@kernel.org>; Paolo Abeni <pabeni@redhat.com>; Simek,
> Michal <michal.simek@amd.com>; Andrew Lunn <andrew@lunn.ch>; Robert
> Hancock <robert.hancock@calian.com>; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org
> Subject: [PATCH v2 1/1] net: axienet: Move reset before DMA detection
>=20
> DMA detection will fail if axinet was started before (by boot loader,

:%s/axinet/axienet/g

> boot ROM, etc). In this state axinet will not start properly.
> XAXIDMA_TX_CDESC_OFFSET + 4 register (MM2S_CURDESC_MSB) is used to
> detect
> 64 DMA capability here. But datasheet says: When DMACR.RS is 1
> (axinet is in enabled state), CURDESC_PTR becomes Read Only (RO) and
> is used to fetch the first descriptor. So iowrite32()/ioread32() trick
> to this register to detect DMA will not work.
> So move axinet reset before DMA detection.
>=20
> Fixes: 04cc2da39698 ("net: axienet: reset core on initialization prior to=
 MDIO

Is this fixes tag correct ? I think the failure is introduced after=20
f735c40ed93c net: axienet: Autodetect 64-bit DMA capability?

> access")
> Signed-off-by: Maxim Kochetkov <fido_max@inbox.ru>
> ---
>  drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
>=20
> diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> index 3e310b55bce2..734822321e0a 100644
> --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> @@ -2042,6 +2042,11 @@ static int axienet_probe(struct platform_device
> *pdev)
>  		goto cleanup_clk;
>  	}
>=20
> +	/* Reset core now that clocks are enabled, prior to accessing MDIO
> */
> +	ret =3D __axienet_device_reset(lp);
> +	if (ret)
> +		goto cleanup_clk;
> +
>  	/* Autodetect the need for 64-bit DMA pointers.
>  	 * When the IP is configured for a bus width bigger than 32 bits,
>  	 * writing the MSB registers is mandatory, even if they are all 0.
> @@ -2096,11 +2101,6 @@ static int axienet_probe(struct platform_device
> *pdev)
>  	lp->coalesce_count_tx =3D XAXIDMA_DFT_TX_THRESHOLD;
>  	lp->coalesce_usec_tx =3D XAXIDMA_DFT_TX_USEC;
>=20
> -	/* Reset core now that clocks are enabled, prior to accessing MDIO
> */
> -	ret =3D __axienet_device_reset(lp);
> -	if (ret)
> -		goto cleanup_clk;
> -
>  	ret =3D axienet_mdio_setup(lp);
>  	if (ret)
>  		dev_warn(&pdev->dev,
> --
> 2.40.1