Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
Feedback-ID: i84414492:Fastmail
User-Agent: Cyrus-JMAP/3.9.0-alpha0-499-gf27bbf33e2-fm-20230619.001-gf27bbf33
Mime-Version: 1.0
Message-Id: <c01ee919-9abb-4796-9ed4-9bb4565dc863@app.fastmail.com>
In-Reply-To: <9132027.CDJkKcVGEf@diego>
References: <20230228215435.3366914-1-heiko@sntech.de>
 <1941316.PYKUYFuaPT@diego>
 <23381fc8-c297-46ed-9e11-a2643e18e4c9@app.fastmail.com>
 <9132027.CDJkKcVGEf@diego>
Date:   Thu, 22 Jun 2023 23:06:44 -0400
From:   "Stefan O'Rear" <sorear@fastmail.com>
To:     "Heiko Stuebner" <heiko@sntech.de>,
        "Palmer Dabbelt" <palmer@dabbelt.com>
Cc:     linux-riscv@lists.infradead.org, samuel@sholland.org,
        guoren@kernel.org, christoph.muellner@vrull.eu,
        conor.dooley@microchip.com, linux-kernel@vger.kernel.org
Subject: Re: [PATCH RFC 2/2] RISC-V: add T-Head vector errata handling
Content-Type: text/plain;charset=utf-8
Content-Transfer-Encoding: quoted-printable
Precedence: bulk

On Thu, Jun 22, 2023, at 4:35 PM, Heiko St=C3=BCbner wrote:
> Am Donnerstag, 22. Juni 2023, 20:58:37 CEST schrieb Stefan O'Rear:
>> Are you aware of "3.7. Vector Fixed-Point Fields in fcsr" in
>> riscv-v-spec-0.7.1.pdf?
>
> oh wow, thanks a lot for that pointer, now I understand your concern.
>
> So in vector-0.7.1 fcsr[10:9] mirrors vxrm and fcsr[8] mirrors vxsat.
>
>
> On a positive note, the T-Head cores seem to not implement the full
> vector 0.7.1 specification after all, in the documentation I have [0]
> fcsr[31:8] are declared as "0" and uppermost bits are [7:5] for the "f=
rm"
> field.

Given that the pdf you linked does not mention any vector CSRs, I am not
confident that it provides a complete and accurate description of vector
functionality in other registers for the C906 with vector extension.

Assuming that you have access to such a chip, I would be much happier wi=
th
the proposed "just a comment" approach if our understanding of the behav=
ior
were confirmed on hardware (specifically: csr_write(CSR_FCSR, 0x700) sho=
uld
not affect csr_read(CSR_VXRM) or csr_read(CSR_VXSAT)).

-s

> So I guess a code comment should suffice to explain :-)
>
>
> Regards
> Heiko
>
>
> [0]=20
> https://github.com/T-head-Semi/openc906/blob/main/doc/%E7%8E%84%E9%93%=
81C906%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C.pdf
> 16.3.1.3 =E6=B5=AE=E7=82=B9=E6=8E=A7=E5=88=B6=E7=8A=B6=E6=80=81=E5=AF=84=
=E5=AD=98=E5=99=A8=EF=BC=88FCSR=EF=BC=89 on page 334