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Date:   Fri, 23 Jun 2023 10:19:08 +0100
From:   Conor Dooley <conor.dooley@microchip.com>
To:     Heiko Stuebner <heiko@sntech.de>
CC:     <palmer@dabbelt.com>, <paul.walmsley@sifive.com>,
        <linux-riscv@lists.infradead.org>, <samuel@sholland.org>,
        <guoren@kernel.org>, <christoph.muellner@vrull.eu>,
        <linux-kernel@vger.kernel.org>,
        Heiko Stuebner <heiko.stuebner@vrull.eu>
Subject: Re: [PATCH v2 2/3] RISC-V: move vector-available status into a
 dedicated variable
Message-ID: <20230623-celestial-vitality-f4a564208b7b@wendy>
References: <20230622231305.631331-1-heiko@sntech.de>
 <20230622231305.631331-3-heiko@sntech.de>
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Hey Heiko,

On Fri, Jun 23, 2023 at 01:13:04AM +0200, Heiko Stuebner wrote:
> From: Heiko Stuebner <heiko.stuebner@vrull.eu>
>=20
> There is at least one core implementing the wrong vector specification,
> which cannot claim to implement the v extension but still is able to
> do vectors similar to v.
>=20
> To not hack around this by claiming to do v, move the has_vector() return
> to act similar to riscv_noncoherent_supported() and move to a separate
> variable that can be set for example from errata code.
>=20
> Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
> ---
>  arch/riscv/include/asm/vector.h | 5 ++++-
>  arch/riscv/kernel/setup.c       | 6 ++++++
>  arch/riscv/kernel/vector.c      | 8 ++++++++
>  3 files changed, 18 insertions(+), 1 deletion(-)
>=20
> diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vec=
tor.h
> index 04c0b07bf6cd..315c96d2b4d0 100644
> --- a/arch/riscv/include/asm/vector.h
> +++ b/arch/riscv/include/asm/vector.h
> @@ -19,13 +19,16 @@
>  #include <asm/csr.h>
>  #include <asm/asm.h>
> =20
> +extern bool riscv_v_supported;
> +void riscv_vector_supported(void);
> +
>  extern unsigned long riscv_v_vsize;
>  int riscv_v_setup_vsize(void);
>  bool riscv_v_first_use_handler(struct pt_regs *regs);
> =20
>  static __always_inline bool has_vector(void)
>  {
> -	return riscv_has_extension_unlikely(RISCV_ISA_EXT_v);
> +	return riscv_v_supported;

Since you're moving this thing away from being backed by an alternative,
should this variable then be marked with something like __ro_after_init?

Cheers,
Conor.

>  }
> =20
>  static inline void __riscv_v_vstate_clean(struct pt_regs *regs)
> diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
> index 971fe776e2f8..952dfb90525e 100644
> --- a/arch/riscv/kernel/setup.c
> +++ b/arch/riscv/kernel/setup.c
> @@ -36,6 +36,7 @@
>  #include <asm/thread_info.h>
>  #include <asm/kasan.h>
>  #include <asm/efi.h>
> +#include <asm/vector.h>
> =20
>  #include "head.h"
> =20
> @@ -308,6 +309,11 @@ void __init setup_arch(char **cmdline_p)
>  	riscv_fill_hwcap();
>  	init_rt_signal_env();
>  	apply_boot_alternatives();
> +
> +	if (IS_ENABLED(CONFIG_RISCV_ISA_V) &&
> +	    riscv_isa_extension_available(NULL, v))
> +		riscv_vector_supported();
> +
>  	if (IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM) &&
>  	    riscv_isa_extension_available(NULL, ZICBOM))
>  		riscv_noncoherent_supported();
> diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c
> index f9c8e19ab301..74178fb71805 100644
> --- a/arch/riscv/kernel/vector.c
> +++ b/arch/riscv/kernel/vector.c
> @@ -22,6 +22,9 @@
> =20
>  static bool riscv_v_implicit_uacc =3D IS_ENABLED(CONFIG_RISCV_ISA_V_DEFA=
ULT_ENABLE);
> =20
> +bool riscv_v_supported;
> +EXPORT_SYMBOL_GPL(riscv_v_supported);
> +
>  unsigned long riscv_v_vsize __read_mostly;
>  EXPORT_SYMBOL_GPL(riscv_v_vsize);
> =20
> @@ -274,3 +277,8 @@ static int riscv_v_init(void)
>  	return riscv_v_sysctl_init();
>  }
>  core_initcall(riscv_v_init);
> +
> +void riscv_vector_supported(void)
> +{
> +	riscv_v_supported =3D true;
> +}
> --=20
> 2.39.2
>=20

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