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Message-ID: <b170cfa5-7b6a-7582-94cb-005de44f7863@quicinc.com>
Date:   Fri, 23 Jun 2023 08:25:23 -0600
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Subject: Re: [PATCH 7/9] clk: qcom: gcc-msm8998: Don't poke at some BIMC GPU
 clocks
Content-Language: en-US
To:     Konrad Dybcio <konrad.dybcio@linaro.org>,
        Andy Gross <agross@kernel.org>,
        Bjorn Andersson <andersson@kernel.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>,
        Taniya Das <tdas@codeaurora.org>
CC:     Marijn Suijten <marijn.suijten@somainline.org>,
        <linux-arm-msm@vger.kernel.org>, <linux-clk@vger.kernel.org>,
        <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>
References: <20230622-topic-8998clk-v1-0-5b7a0d6e98b1@linaro.org>
 <20230622-topic-8998clk-v1-7-5b7a0d6e98b1@linaro.org>
From:   Jeffrey Hugo <quic_jhugo@quicinc.com>
In-Reply-To: <20230622-topic-8998clk-v1-7-5b7a0d6e98b1@linaro.org>
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Precedence: bulk

On 6/22/2023 5:57 AM, Konrad Dybcio wrote:
> Linux should apparently not be concerned with gcc_gpu_bimc_gfx_src_clk and
> gcc_gpu_bimc_gfx_src_clk on MSM8998, as they're preconfigured for us.
> Unregister them to prevent issues.

You mention the bimc_gfx clock twice here.  One of them has to be a typo.

Also, can you clarify the reasoning?  The RCG is controlled by the RPM, 
but the branch clock is under the control of Linux.

> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>   drivers/clk/qcom/gcc-msm8998.c | 28 ----------------------------
>   1 file changed, 28 deletions(-)
> 
> diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c
> index ef410f52f09f..980b5a1b58ae 100644
> --- a/drivers/clk/qcom/gcc-msm8998.c
> +++ b/drivers/clk/qcom/gcc-msm8998.c
> @@ -2136,19 +2136,6 @@ static struct clk_branch gcc_gpu_bimc_gfx_clk = {
>   	},
>   };
>   
> -static struct clk_branch gcc_gpu_bimc_gfx_src_clk = {
> -	.halt_reg = 0x7100c,
> -	.halt_check = BRANCH_HALT,
> -	.clkr = {
> -		.enable_reg = 0x7100c,
> -		.enable_mask = BIT(0),
> -		.hw.init = &(struct clk_init_data){
> -			.name = "gcc_gpu_bimc_gfx_src_clk",
> -			.ops = &clk_branch2_ops,
> -		},
> -	},
> -};
> -
>   static struct clk_branch gcc_gpu_cfg_ahb_clk = {
>   	.halt_reg = 0x71004,
>   	.halt_check = BRANCH_HALT_SKIP,
> @@ -2168,19 +2155,6 @@ static struct clk_branch gcc_gpu_cfg_ahb_clk = {
>   	},
>   };
>   
> -static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
> -	.halt_reg = 0x71018,
> -	.halt_check = BRANCH_HALT,
> -	.clkr = {
> -		.enable_reg = 0x71018,
> -		.enable_mask = BIT(0),
> -		.hw.init = &(struct clk_init_data){
> -			.name = "gcc_gpu_snoc_dvm_gfx_clk",
> -			.ops = &clk_branch2_ops,
> -		},
> -	},
> -};
> -
>   static struct clk_branch gcc_hmss_ahb_clk = {
>   	.halt_reg = 0x48000,
>   	.halt_check = BRANCH_HALT_VOTED,
> @@ -3032,9 +3006,7 @@ static struct clk_regmap *gcc_msm8998_clocks[] = {
>   	[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
>   	[GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
>   	[GCC_GPU_BIMC_GFX_CLK] = &gcc_gpu_bimc_gfx_clk.clkr,
> -	[GCC_GPU_BIMC_GFX_SRC_CLK] = &gcc_gpu_bimc_gfx_src_clk.clkr,
>   	[GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
> -	[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
>   	[GCC_HMSS_AHB_CLK] = &gcc_hmss_ahb_clk.clkr,
>   	[GCC_HMSS_AT_CLK] = &gcc_hmss_at_clk.clkr,
>   	[GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,
>