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From:   Huacai Chen <chenhuacai@kernel.org>
Date:   Sat, 24 Jun 2023 00:03:16 +0800
Message-ID: <CAAhV-H6=yLvVdyOCdjFWrUe_MbG6PymTn5=o2rQOrpXLzcvhdQ@mail.gmail.com>
Subject: Re: [PATCH 4/9] LoongArch: Make {read,write}_fcsr compatible with LLVM/Clang
To:     WANG Xuerui <kernel@xen0n.name>
Cc:     WANG Rui <wangrui@loongson.cn>, Xi Ruoyao <xry111@xry111.site>,
        loongarch@lists.linux.dev, linux-kbuild@vger.kernel.org,
        llvm@lists.linux.dev, linux-kernel@vger.kernel.org,
        WANG Xuerui <git@xen0n.name>
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Hi, Xuerui,

On Fri, Jun 23, 2023 at 9:44=E2=80=AFPM WANG Xuerui <kernel@xen0n.name> wro=
te:
>
> From: WANG Xuerui <git@xen0n.name>
>
> LLVM/Clang does not see FCSRs as GPRs, so make use of compiler
> built-ins instead for better maintainability with less code.
>
> The existing version cannot be wholly removed though, because the
> built-ins, while available on GCC too, is predicated TARGET_HARD_FLOAT,
> which means soft-float code cannot make use of them.
>
> Signed-off-by: WANG Xuerui <git@xen0n.name>
> ---
>  arch/loongarch/include/asm/loongarch.h | 19 +++++++++++++------
>  1 file changed, 13 insertions(+), 6 deletions(-)
>
> diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/incl=
ude/asm/loongarch.h
> index ac83e60c60d1..eedc313b5241 100644
> --- a/arch/loongarch/include/asm/loongarch.h
> +++ b/arch/loongarch/include/asm/loongarch.h
> @@ -1445,12 +1445,6 @@ __BUILD_CSR_OP(tlbidx)
>  #define EXCCODE_INT_START      64
>  #define EXCCODE_INT_END                (EXCCODE_INT_START + EXCCODE_INT_=
NUM - 1)
>
> -/* FPU register names */
> -#define LOONGARCH_FCSR0        $r0
> -#define LOONGARCH_FCSR1        $r1
> -#define LOONGARCH_FCSR2        $r2
> -#define LOONGARCH_FCSR3        $r3
> -
>  /* FPU Status Register Values */
>  #define FPU_CSR_RSVD   0xe0e0fce0
>
> @@ -1487,6 +1481,18 @@ __BUILD_CSR_OP(tlbidx)
>  #define FPU_CSR_RU     0x200   /* towards +Infinity */
>  #define FPU_CSR_RD     0x300   /* towards -Infinity */
>
> +#ifdef CONFIG_CC_IS_CLANG
> +#define LOONGARCH_FCSR0        0
> +#define LOONGARCH_FCSR1        1
> +#define LOONGARCH_FCSR2        2
> +#define LOONGARCH_FCSR3        3
> +#define read_fcsr(source)      __movfcsr2gr(source)
> +#define write_fcsr(dest, val)  __movgr2fcsr(dest, val)
> +#else /* CONFIG_CC_IS_CLANG */
> +#define LOONGARCH_FCSR0        $r0
> +#define LOONGARCH_FCSR1        $r1
> +#define LOONGARCH_FCSR2        $r2
> +#define LOONGARCH_FCSR3        $r3
>  #define read_fcsr(source)      \
>  ({     \
>         unsigned int __res;     \
Now the latest binutils also supports $fcsr, so I suggest to always
use inline asm, and change CONFIG_CC_IS_CLANG to
CONFIG_AS_HAS_FCSR_CLASS. And of course, Patch3 and Patch4 can be
merged then.

Huacai

> @@ -1503,5 +1509,6 @@ do {      \
>         "       movgr2fcsr      "__stringify(dest)", %0 \n"     \
>         : : "r" (val)); \
>  } while (0)
> +#endif /* CONFIG_CC_IS_CLANG */
>
>  #endif /* _ASM_LOONGARCH_H */
> --
> 2.40.0
>